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Streamline verification process with formal property verification to meet highly compressed design cycle
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 42nd annual Design Automation Conference table of contents
Anaheim, California, USA
SESSION: Special session: formally verifying your 10-million gate design table of contents
Pages: 674 - 677  
Year of Publication: 2005
ISBN:1-59593-058-2
Author
Prosenjit Chatterjee  NVIDIA Corporation, Santa Clara, CA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 11,   Citation Count: 2
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ABSTRACT

In this paper, I describe a methodology and tool flow for using formal verification effectively to reduce the verification burden in large custom ASIC designs.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Malachowsky, C., "When 10M Gates Just Isn't Enough: The GPU Challenge", DAC, 2002.
 
2
Smith, D., "NVIDIA: Scaling metholodogy", Proceedings of EDP, 2002.
 
3
Magellan product description web site, http://www.synopsys.com/products/magellan/magellan.html, 2005.
 
4
Ibid.
 
5
Ip, N., and Foster, H., "Design Illumination". DesignCon 2005.
 
6
Jasper Design Automation, "JasperGold 3.1 Reference


Collaborative Colleagues:
Prosenjit Chatterjee: colleagues