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Architecture-adaptive range limit windowing for simulated annealing FPGA placement
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 42nd annual Design Automation Conference table of contents
Anaheim, California, USA
SESSION: CAD for FPGAs table of contents
Pages: 439 - 444  
Year of Publication: 2005
ISBN:1-59593-058-2
Authors
Ken Eguro  University of Washington, Seattle, WA
Scott Hauck  University of Washington, Seattle, WA
Akshay Sharma  University of Washington, Seattle, WA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control the acceptance ratio of swaps during placement. However, the implementation of such a system is not necessarily obvious. Existing range limiting techniques have several fundamental shortcomings when dealing with both standard island-style FPGAs and more exotic architectures. In this paper we discuss the nature of these problems and present a new algorithm that attempts to deal with these issues.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Eguro, K. and S. Hauck, "Issues of Wirelength Cost Models in Routing-Constrained FPGAs", University of Washington, Dept. of EE Technical Report UWEETR-2004-0006, 2004.
 
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Collaborative Colleagues:
Ken Eguro: colleagues
Scott Hauck: colleagues
Akshay Sharma: colleagues