| Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 42nd annual Design Automation Conference
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Anaheim, California, USA
SESSION: Performance, energy, and fault-tolerance considerations for MPSoC designs
table of contents
Pages: 266 - 269
Year of Publication: 2005
ISBN:1-59593-058-2
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Downloads (6 Weeks): 17, Downloads (12 Months): 62, Citation Count: 6
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ABSTRACT
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmission of messages, such that designerimposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statically assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. Firstly, we reduce the total amount of transmitted messages, and, secondly, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arrival probability and guaranteed worst case application response time.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 6
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Srinivasan Murali , David Atienz , Luca Benini , Giovanni De Michel, A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Antonio Pullini , Federico Angiolini , Paolo Meloni , David Atienza , Srinivasan Murali , Luigi Raffo , Giovanni De Micheli , Luca Benini, NoC Design and Implementation in 65nm Technology, Proceedings of the First International Symposium on Networks-on-Chip, p.273-282, May 07-09, 2007
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