| Simulation based deadlock analysis for system level designs |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 42nd annual Design Automation Conference
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Anaheim, California, USA
SESSION: Performance, energy, and fault-tolerance considerations for MPSoC designs
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Pages: 260 - 265
Year of Publication: 2005
ISBN:1-59593-058-2
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Authors
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Xi Chen
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University of California, Riverside, CA
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Abhijit Davare
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University of California, Berkeley, CA
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Harry Hsieh
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University of California, Riverside, CA
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Alberto Sangiovanni-Vincentelli
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University of California, Berkeley, CA
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Yosinori Watanabe
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Cadence Berkeley Laboratories, Berkeley, CA
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Downloads (6 Weeks): 3, Downloads (12 Months): 46, Citation Count: 0
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ABSTRACT
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the synchronization dependencies in concurrent systems modeled in the Metropolis design environment, where system functions, high level architectures and function-architecture mappings can be modeled and simulated. We propose a data structure called the dynamic synchronization dependency graph, which captures the runtime (blocking) dependencies. A loop-detection algorithm is then used to detect deadlocks and help designers quickly isolate and identify modeling errors that cause the deadlock problems. We demonstrate our approach through a real world design example, which is a complex functional model for video processing and a high level model of function-architecture mapping.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Felice Balarin , Jerry Burch , Luciano Lavagno , Yosinori Watanabe , Roberto Passerone , Alberto Sangiovanni-Vincentelli, Constraints Specification at Higher Levels of Abstraction, Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01), p.129, December 07-09, 2001
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Felice Balarin , Yosinori Watanabe , Harry Hsieh , Luciano Lavagno , Claudio Passerone , Alberto Sangiovanni-Vincentelli, Metropolis: An Integrated Electronic System Design Environment, Computer, v.36 n.4, p.45-52, April 2003
[doi> 10.1109/MC.2003.1193228]
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K. Keutzer, S. Malik, A. R. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli. System level design: orthogonalization of concerns and platform-based design. IEEE Transactions on Computer-Aided Design, 19(12):1523--1543, Dec. 2000.
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Murali Krishnamurthi , Amar Basavatia , Sanjeev Thallikar, Deadlock detection and resolution in simulation models, Proceedings of the 26th conference on Winter simulation, p.708-715, December 11-14, 1994, Orlando, Florida, United States
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J. L. Peterson and A. Silbershatz. Operating System Concepts. Addison-Wesley, 1983.
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