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A pattern matching coprocessor for network security
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 42nd annual Design Automation Conference table of contents
Anaheim, California, USA
SESSION: Architectures for cryptography and security applications table of contents
Pages: 234 - 239  
Year of Publication: 2005
ISBN:1-59593-058-2
Authors
Young H. Cho  University of California, Los Angeles, Los Angeles, CA
William H. Mangione-Smith  University of California, Los Angeles, Los Angeles, CA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 21,   Downloads (12 Months): 113,   Citation Count: 12
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ABSTRACT

It has been estimated that computer network worms and virus caused the loss of over $55B in 2003. Network security system use techniques such as deep packet inspection to detect the harmful packets. While software intrusion detection system running on general purpose processors can be updated in response to new attacks. They lack the processing power to monitor gigabit networks. We present a high performance pattern matching co-processor architecture that can be used to monitor and identify a large number of intrusion signature. The design consists of a bank of pattern matchers that are used to implement a highly concurrent filter. The pattern matchers can be programmed to match multiple patterns of various lengths, and are able to leverage the existing databases of threat signatures. We have been able to program the filters to match all the payload patterns defined in the widely used Snort network intrusion detection system at a rate above 7 Gbps, with memory space left to accommodate threat signatures that become available in the future.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Neil Desi, "Increasing Performance in High Speed NIDS: A look at Snort's Internals," Feb 2002.
 
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Ioannis Sourdis and Dionisios Pnevmatikatos, "Fast, Large-Scale String Match for a 10Gbps FPGA-based Network Intrusion Detection System," in 13th Conference on Field Programmable Logic and Applications, Lisbon, Portugal, September 2003, Springer-Verlag.
 
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J.W. Lockwood, J. Moscola, M. Kulig, D. Reddick, and T. Brooks, "Internet Worm and Virus Protection in Dynamically Reconfigurable Hardware," in Military and Aerospace Programmable Logic Device (MAPLD), Washington DC, September 2003, NASA Office of Logic Design.
 
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Young H. Cho and William H. Mangione-Smith, "Programmable Hardware for Deep Packet Filtering on a Large Signature Set," in First IBM Watson P=ac2 Conference, Yorktown, NY, October 2004, IBM.
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CITED BY  12

Collaborative Colleagues:
Young H. Cho: colleagues
William H. Mangione-Smith: colleagues