Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions

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Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 42nd annual Design Automation Conference table of contents

Anaheim, California, USA

SESSION: Statistical timing analysis table of contents

Pages: 71 - 76

Year of Publication: 2005

ISBN:1-59593-058-2

Authors

Hongliang Chang	University of Minnesota
Vladimir Zolotov	IBM T.J.W. Research Center, Yorktown Heights, NY
Sambasivan Narayan	IBM Systems & Technology, Essex Junction, VT
Chandu Visweswariah	IBM T.J.W. Research Center, Yorktown Heights, NY

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 69, Citation Count: 47

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ABSTRACT

Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical static timing analysis (statistical STA) has been proposed as a solution. Unfortunately, the existing approaches either do not consider explicit gate delay dependence on process parameters [3] - [6] or restrict analysis to linear Gaussian parameters only [1, [2]. Here we extend the capabilities of parameterized block-based statistical STA [1] to handle nonlinear function of delays and non-Gaussian parameters, while retaining maximum efficiency of processing linear Gaussian parameters. Our novel technique improves accuracy in predicting circuit timing characteristics and retains such benefits of parameterized block-based statistical STA as an incremental mode of operation, computation of criticality probabilities and sensitivities to process parameter variations. We implemented our technique in an industrial statistical timing analysis tool. Our experiments with large digital blocks showed both efficiency and accuracy of the proposed technique.

REFERENCES

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	1	C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996663]
	2	Hongliang Chang , Sachin S. Sapatnekar, Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.621, November 09-13, 2003 [doi>10.1109/ICCAD.2003.129]
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	5	Anirudh Devgan , Chandramouli Kashyap, Block-based Static Timing Analysis with Uncertainty, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.607, November 09-13, 2003 [doi>10.1109/ICCAD.2003.41]
	6	A. Agarwal, V. Zolotov and D. Blaauw, "Statistical timing analysis using bounds and selective enumeration," IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 22, no. 9, Sept 2003, pp.1243--1260.
	7	Sarvesh Bhardwaj , Sarma B. K. Vrudhula , David Blaauw, "AU: Timing Analysis Under Uncertainty, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.615, November 09-13, 2003 [doi>10.1109/ICCAD.2003.1]
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