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Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 42nd annual Design Automation Conference table of contents
Anaheim, California, USA
SESSION: Microarchitecture-level power analysis and optimization techniques table of contents
Pages: 27 - 30  
Year of Publication: 2005
ISBN:1-59593-058-2
Authors
Patrick Schaumont  UCLA, CA
Bo-Cheng Charles Lai  UCLA, CA
Wei Qin  Boston University, MA
Ingrid Verbauwhede  UCLA, CA and ESAT, K.U. Leuven, BE
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 19,   Citation Count: 5
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ABSTRACT

We propose an embedded multiprocessor architecture and its associated thread-based programming model. Using a cycle-true simulation model of this architecture, we are able to estimate energy savings for a threaded C program. The savings are obtained by voltage- and frequency-scaling of the individual processors. We port a fingerprint minutiae detection application onto this architecture, and show the resulting performance on single-, dual-, and quad-processor configurations. The energy-scaled quadprocessor version results in a 77% energy reduction over the single-processor non-scaled implementation, at only a 2.2% degradation in cycle count.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J. Goodacre, "Challenges in programming multiprocessor platforms," 4th International seminar on Application-Specific MPSOC, France, 2004.
 
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A. Jerraya, W. Wolf, "Multiprocessor Systems-on-Chips," Morgan Kaufmann, Sept 2004, ISBN 0-12-385251-X.
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J. Rabaey, "Power Management in Wireless SOCs," 4th International seminar on Application-Specific MPSOC, France, 2004.
 
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D. Keppel, "Tools and Techniques for Building Fast Portable Threads Packages," UWCSE 93-05-06, U. Washington, 1993.
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S. Yang, K. Sakiyama, I. Verbauwhede, "A compact and efficient fingerprint verification system for secure embedded systems," 37th Asilomar Conference, Nov 2003:2058--2062.
 
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C. Ussery, " Method of generating application specific integrated circuits using a programmable hardware architecture," US. Pat. 6,075,935, 12/1/1997.
 
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Collaborative Colleagues:
Patrick Schaumont: colleagues
Bo-Cheng Charles Lai: colleagues
Wei Qin: colleagues
Ingrid Verbauwhede: colleagues