|
ABSTRACT
Development of highly reliable and available systems requires consideration of the occurrence of single event upsets, the effects they have on system performance, and strategies for their prevention and mitigation. Methods of systems engineering process and the application and validation of techniques for fault tolerance are discussed as elements in the elimination and mitigation of single event upsets.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Bossen, D., CMOS Soft Errors and Server Design, Radiation Induced Soft Errors in Silicon Components and Computer Systems Tutorial, IRPS 2002.
|
| |
2
|
Johnston, A., Mitigation Methods for Soft Errors and Related Radiation Effects in Spacecraft, Radiation Induced Soft Errors in Silicon Components and Computer Systems Tutorial, IRPS 2002.
|
| |
3
|
Dodd, P. and Sexton, F., Mitigation of Single- Event Effects in Mission- Critical Systems, Radiation Induced Soft Errors in Silicon Components and Computer Systems Tutorial, IRPS 2002.
|
| |
4
|
Normand, E., Single-Event Effects in Avionics, IEEE Transactions on Nuclear Science, Vol. 43, No. 2, April 1996, Page 461--474.
|
| |
5
|
National Geophysical Data Center (NGDC), National Oceanic and Atmospheric Administration (NOAA), http://www.ngds.noaa.gov/stp/SOLAR/COSMIC_RAYS/cosmic.html
|
| |
6
|
LaBel, K., Michele Gates, M., Barth, J., Stassinopoulos, E.G., Johnston, A. and Marshall, P., Single Event Criticality Analysis (SEECA), http://flick.gsfc.nasa.gov/radhome/papers
|
| |
7
|
|
| |
8
|
|
| |
9
|
|
| |
10
|
Mitsubishi Electric Develops High-Frequency Synchronous SRAM with Dramatically Reduced Soft Error Rate, International Solid-State Circuits Conference, Feb 1999, http://www.mitsubishichips.com/press/releases/fsram_99.htm
|
| |
11
|
Vinson, J, Circuit Reliability of Memory Cells with SEU Protection, IEEE Transactions on Nuclear Science, Vol. 39, No. 6, pp 1671--1678, (December 1992).
|
| |
12
|
Rockett, L., An SEU Hardened CMOS Data Latch Design, IEEE Transactions on Nuclear Science, Vol. 35, No. 6, pp 1682--1687, (December 1992).
|
| |
13
|
Calin, T., Nicolaidis, M., Velazco, R., Upset Hardened Memory Design for Submicron CMOS Technology, IEEE Transactions on Nuclear Science, Vol. 43, No. 6, pp 2874--2878, (December 1996).
|
| |
14
|
Norely, M., Liu, and Whitaker, S., Low Power SEU Immune CMOS Memory Circuits, IEEE Transactions on Nuclear Science, Vol. 39, No. 6, pp 1679--1684, (December 1992).
|
| |
15
|
|
| |
16
|
|
| |
17
|
Chen, I. and Yen, I., Analysis of Probablistic Error Checking Procedures on Storage Systems, The Computer Journal, Vol. 38, No. 5, (1995).
|
| |
18
|
Peercy, M. and Banerjee, P., Fault Tolerant VSLI Systems, Proceedings of the IEEE, pp 745--758, (1993).
|
| |
19
|
|
| |
20
|
Mavis, D. and Eaton, P., Temporally Redundant Latch for Preventing Single Event Disruptions in Sequential Integrated Circuits, Mission Research Corporation Technical Report P8111.29, October 1998.
|
| |
21
|
|
| |
22
|
|
| |
23
|
Banatre, M. and Lee, P., Hardware and Software Architectures for Fault Tolerance, Experiences and Perspectives.
|
| |
24
|
Kim, K.H., and Welch, H.O., Distributed Execution of Recovery Blocks: An Approach for Uniform Treatment of Hardware and Software Faults in Real-Time Applications, Fault-Tolerance Systems: Techniques and Applications, edited by Hoang Phan, pp 95--105, (1992).
|
| |
25
|
Blaquiere, Y., Gagne, G., Savaria, Y., and Evequoz, C., A New Efficient Algorithm-Based SEU Tolerant System Architecture, IEEE Transactions on Nuclear Science, Vol. 42, No. 6, (Dec 1995)
|
INDEX TERMS
Primary Classification:
B.
Hardware
B.8
Performance and Reliability
B.8.1
Reliability, Testing, and Fault-Tolerance
General Terms:
Reliability
Keywords:
error detection and correction coding,
fault avoidance,
fault masking,
fault tolerant systems,
modular redundancy,
radiation effects,
single event upset,
soft error rate,
temporal redundancy
|