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Locally decodable codes with 2 queries and polynomial identity testing for depth 3 circuits
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Source Annual ACM Symposium on Theory of Computing archive
Proceedings of the thirty-seventh annual ACM symposium on Theory of computing table of contents
Baltimore, MD, USA
SESSION: Session 12A table of contents
Pages: 592 - 601  
Year of Publication: 2005
ISBN:1-58113-960-8
Authors
Zeev Dvir  Weizmann Institute of Science, Rehovot, Israel
Amir Shpilka  Weizmann Institute of Science, Rehovot, Israel
Sponsors
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this work we study two, seemingly unrelated, notions. Locally Decodable Codes (LDCs) are codes that allow the recovery of each message bit from a constant number of entries of the codeword. Polynomial Identity Testing (PIT) is one of the fundamental problems of algebraic complexity: we are given a circuit computing a multivariate polynomial and we have to determine whether the polynomial is identically zero. We improve known results on locally decodable codes and on polynomial identity testing and show a relation between the two notions. In particular we obtain the following results:

  1. We show that if E: Fn → Fm is a linear LDC with 2 queries then m = exp(Ω(n)). Previously this was only known for fields of size << 2n [18].
  2. We show that from every depth 3 arithmetic circuit (ΣΠΣ circuit), C, with a bounded (constant) top fan-in that computes the zero polynomial, one can construct a locally decodeable code. More formally: Assume that C is minimal (no subset of the multiplication gates sums to zero) and simple (no linear function appears in all the multiplication gates). Denote by d the degree of the polynomial computed by C and by r the rank of the linear functions appearing in C. Then we can construct a linear LDC with 2 queries, that encodes messages of length r/polylog(d) by codewords of length O(d).
  3. We prove a structural theorem for ΣΠΣ circuits, with a bounded top fan-in, that compute the zero polynomial. In particular we show that if such a circuit is simple and minimal and of polynomial size then its rank, r, is only polylogarithmic in the number of variables (a priory it could have been linear).
  4. We give new PIT algorithms for ΣΠΣ circuits with a bounded top fan-in:
    1. A deterministic algorithm that runs in quasi polynomial time.
    2. A randomized algorithm that runs in polynomial time and uses only polylogarithmic number of random bits.
.Moreover, when the circuit is multilinear our deterministic algorithm runs in polynomial time. Previously, deterministic subexponential time algorithms for PIT in bounded depth circuits were known only for depth 2 circuits (in the black box model)[22, 9, 28]. In particular, for the special case of depth 3 circuits with 3 multiplication gates our result resolves an open question asked by Klivans and Spielman [28].


REFERENCES

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