|
ABSTRACT
Most general-purpose processors provide support for memory pages of large sizes, called superpages. Superpages enable each entry in the translation lookaside buffer (TLB) to map a large physical memory region into a virtual address space. This dramatically increases TLB coverage, reduces TLB misses, and promises performance improvements for many applications. However, supporting superpages poses several challenges to the operating system, in terms of superpage allocation and promotion tradeoffs, fragmentation control, etc. We analyze these issues, and propose the design of an effective superpage management system. We implement it in FreeBSD on the Alpha CPU, and evaluate it on real workloads and benchmarks. We obtain substantial performance benefits, often exceeding 30%; these benefits are sustained even under stressful workload scenarios.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
D. Bailey, T. Harris, W. Saphir, R. van der Wijngaart, A. Woo, and M. Yarrow. The NAS Parallel Benchmarks 2.0. Report NAS-95-020, NASA Ames Research Center, Moffett Field, CA, 1995.
|
 |
2
|
|
| |
3
|
|
| |
4
|
FIPS 180-1. Secure Hash Standard. Technical Report Publication 180-1, Federal Information Processing Standard (FIPS), National Institute of Standards and Technology, US Department of Commerce, Washington D. C., Apr. 1995.
|
| |
5
|
M. Frigo and S. G. Johnson. FFTW: An adaptive software architecture for the FFT. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, volume 3, Seattle, WA, May 1998.
|
| |
6
|
N. Ganapathy and C. Schimmel. General purpose operating system support for multiple page sizes. In Proceedings of the USENIX 1998 Annual Technical Conference, Berkeley, CA, June 1998.
|
| |
7
|
|
| |
8
|
Imagemagick. http://www.imagemagick.org.
|
 |
9
|
|
| |
10
|
|
 |
11
|
|
| |
12
|
Y. A. Khalidi, M. Talluri, M. N. Nelson, and D. Williams. Virtual memory support for multiple page sizes. In Proceedings of the Fourth IEEE Workshop on Workstation Operating Systems, Napa, CA, Oct. 1993.
|
| |
13
|
J. C. Mogul. Big memories on the desktop. In Proceedings of the Fourth IEEE Workshop on Workstation Operating Systems, Napa, CA, Oct. 1993.
|
 |
14
|
|
| |
15
|
J. Poskanzer. thttpd - tiny/turbo/throttling HTTP server. http://www.acme.com/software/thttpd/.
|
 |
16
|
Theodore H. Romer , Wayne H. Ohlrich , Anna R. Karlin , Brian N. Bershad, Reducing TLB and memory overhead using online superpage promotion, Proceedings of the 22nd annual international symposium on Computer architecture, p.176-187, June 22-24, 1995, S. Margherita Ligure, Italy
|
 |
17
|
M. Rosenblum , E. Bugnion , S. A. Herrod , E. Witchel , A. Gupta, The impact of architectural trends on operating system performance, Proceedings of the fifteenth ACM symposium on Operating systems principles, p.285-298, December 03-06, 1995, Copper Mountain, Colorado, United States
|
| |
18
|
|
| |
19
|
I. Subramanian, C. Mather, K. Peterson, and B. Raghunath. Implementation of multiple pagesize support in HP-UX. In Proceedings of the USENIX 1998 Annual Technical Conference, Berkeley, CA, June 1998.
|
 |
20
|
|
 |
21
|
M. Talluri , M. D. Hill , Y. A. Khalidi, A new page table for 64-bit address spaces, Proceedings of the fifteenth ACM symposium on Operating systems principles, p.184-200, December 03-06, 1995, Copper Mountain, Colorado, United States
|
 |
22
|
Madhusudhan Talluri , Shing Kong , Mark D. Hill , David A. Patterson, Tradeoffs in supporting two page sizes, Proceedings of the 19th annual international symposium on Computer architecture, p.415-424, May 19-21, 1992, Queensland, Australia
|
 |
23
|
Richard Uhlig , David Nagle , Tim Stanley , Trevor Mudge , Stuart Sechrest , Richard Brown, Design tradeoffs for software-managed TLBs, ACM Transactions on Computer Systems (TOCS), v.12 n.3, p.175-205, Aug. 1994
[doi> 10.1145/185514.185515]
|
 |
24
|
D. A. Wood , S. J. Eggers , G. Gibson , M. D. Hill , J. M. Pendleton, An in-cache address translation mechanism, Proceedings of the 13th annual international symposium on Computer architecture, p.358-365, June 02-05, 1986, Tokyo, Japan
|
CITED BY 9
|
|
|
|
|
Nikolai Joukov , Aditya Kashyap , Gopalan Sivathanu , Erez Zadok, An electric fence for kernel buffers, Proceedings of the 2005 ACM workshop on Storage security and survivability, November 11-11, 2005, Fairfax, VA, USA
|
|
|
|
|
|
|
|
|
Jinzhan Peng , Guei-Yuan Lueh , Gansha Wu , Xiaogang Gou , Ryan Rakvic, A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems, Proceedings of the 2006 workshop on Memory system performance and correctness, October 22-22, 2006, San Jose, California
|
|
|
|
|
|
|
|
|
Ted Huffmire , Brett Brotherton , Nick Callegari , Jonathan Valamehr , Jeff White , Ryan Kastner , Tim Sherwood, Designing secure systems on reconfigurable hardware, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.3, p.1-24, July 2008
|
|
|
|
|