Energy-efficient datapath scheduling using multiple voltages and dynamic clocking

ABSTRACT

Recently, dynamic frequency scaling has been explored at the CPU and system levels for power optimization. Low-power datapath scheduling using multiple supply voltages has been well researched. In this work, we develop new datapath scheduling algorithms that use multiple supply voltages and dynamic frequency clocking in a coordinated manner in order to reduce the energy consumption of datapath circuits. In dynamic frequency clocking, the functional units can be operated at different frequencies depending on the computations occurring within the datapath during a given clock cycle. The strategy is to schedule high-energy units, such as multipliers at lower frequencies, so that they can be operated at lower voltages to reduce energy consumption and the low-energy units, such as adders at higher frequencies, to compensate for speed. The proposed time- and resource-constrained algorithms have been applied to various high-level synthesis benchmark circuits under different time and resource constraints. The experimental results show significant reduction in energy for both the algorithms.

REFERENCES

• 1: A. Antola , V. Piuri , M. Sami, A low-redundancy approach to semi-concurrent error detection in data paths, Proceedings of the conference on Design, automation and test in Europe, p.266-272, February 23-26, 1998, Le Palais des Congrés de Paris, France
• 2: Benini, L., Macii, E., Pnocino, M., and Micheli, G. D. 1998. Telescopic units : A new paradigm for performance optimization of VLSI design. IEEE Trans. Comput.-Aid. Des. Integrat. Circ. Syst. 17, 3 (Mar.), 220--232.
• 3: L. Benini , G. De Micheli , A. Lioy , E. Macii , G. Odasso , M. Poncino, Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting, IEEE Transactions on Computers, v.48 n.8, p.769-779, August 1999 [doi>10.1109/12.795120]
• 4: Brynjolfson, I. and Zilic, Z. 2000a. Dynamic clock management for low power applications in FPGAs. In Proceedings of the IEEE Custom Integrated Circuits Conference. 139--142.
• 5: Ian Brynjolfson , Zeljko Zilic, FPGA clock management for low power applications (poster abstract), Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.219, February 10-11, 2000, Monterey, California, United States [doi>10.1145/329166.329216]
• 6: T. D. Burd , R. W. Brodersen, Energy efficient CMOS microprocessor design, Proceedings of the 28th Hawaii International Conference on System Sciences (HICSS'95), p.288, January 04-07, 1995
• 7: Burd, T., Pering, T. A., Stratakos, A. J., and Brodersen, R. W. 2000. A dynamic voltage scaled microprocessor system. IEEE J. Solid-State Circ. 35, 11 (Nov.), 1571--1580.
• 8: Jui-Ming Chang , Massoud Pedram, Energy minimization using multiple supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.436-443, Dec. 1997 [doi>10.1109/92.645070]
• 9: Fetweis, G., Chiu, J., and Fraenkel, B. 1993. A low-complexity bit-serial DCT/IDCT architecture. In Proceedings of the IEEE International Conference on Communications. 217--221.
• 10: Grunwald, D., Levis, P., and Farkas, K. I. 2000. Policies for dynamic clock scheduling. In Proceedings of the 2000 Operating Systems Design and Implementation.
• 11: Chung-Hsing Hsu , Ulrich Kremer , Michael Hsiao, Compiler-Directed Dynamic Frequency and Voltage Scheduling, Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers, p.65-81, November 12, 2000
• 12: Mark C. Johnson , Kaushik Roy, Datapath scheduling with multiple supply voltages and level converters, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.3, p.227-248, July 1997 [doi>10.1145/264995.264997]
• 13: Kim, J. M. and Chae, S. I. 1996. New MPEG2 decoder architecture using frequency scaling. In Proceedings of the IEEE International Symposium on Circuits and Systems. 253--256.
• 14: Kollig, P. and Al-Hashimi, B. M. 1997. Simultaneous scheduling, allocation and binding in high level synthesis. IEE Electron. Lett. 33, 18 (Aug.), 1516--1518.
• 15: Kumar, A. and Bayoumi, M. 1999. Multiple voltage-based scheduling methodology for low power in the high level synthesis. In Proceedings of the International Symposium on Circuits and Systems (Vol. 1). 371--379.
• 16: Yann-Rue Lin , Cheng-Tsung Hwang , Allen C.-H. Wu, Scheduling techniques for variable voltage low power designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.81-97, April 1997 [doi>10.1145/253052.253054]
• 17: Ali Manzak , Chaitali Chakrabarti, A low power scheduling scheme with resources operating at multiple voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.6-14, 2/1/2002 [doi>10.1109/92.988725]
• 18: Thomas L. Martin , Daniel P. Siewiorek, Nonideal battery and main memory effects on CPU speed-setting for low power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.1, p.29-34, Feb. 2001 [doi>10.1109/92.920816]
• 19: Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
• 20: Saraju P. Mohanty , N. Ranganathan, Energy Efficient Scheduling for Datapath Synthesis, Proceedings of the 16th International Conference on VLSI Design, p.446, January 04-08, 2003
• 21: Mohanty, S. P., Ranganathan, N., and Chappidi, S. K. 2003. An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. In Proceedings of the International Symposium on Circuits and Systems (Vol. 5). 313--316.
• 22: Datapath Scheduling using Dynamic Frequency Clocking, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, p.65, April 25-26, 2002
• 23: José Monteiro , Srinivas Devadas , Pranav Ashar , Ashutosh Mauskar, Scheduling techniques to enable power management, Proceedings of the 33rd annual conference on Design automation, p.349-352, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240584]
• 24: E. Musoll , J. Cortadella, Scheduling and resource binding for low power, Proceedings of the 8th international symposium on System synthesis, p.104-109, September 13-15, 1995, Cannes, France [doi>10.1145/224486.224523]
• 25: C. A. Papachristou , H. Konuk, A linear program driven scheduling and allocation method followed by an interconnect optimization algorithm, Proceedings of the 27th ACM/IEEE conference on Design automation, p.77-83, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123231]
• 26: Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996 [doi>10.1145/225871.225877]
• 27: Trevor Pering , Thomas Burd , Robert Brodersen, Voltage scheduling in the IpARM microprocessor system, Proceedings of the 2000 international symposium on Low power electronics and design, p.96-101, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344530]
• 28: Johan Pouwelse , Koen Langendoen , Henk Sips, Dynamic voltage scaling on a low-power microprocessor, Proceedings of the 7th annual international conference on Mobile computing and networking, p.251-259, July 2001, Rome, Italy [doi>10.1145/381677.381701]
• 29: Johan Pouwelse , Koen Langendoen , Henk Sips, Energy priority scheduling for variable voltage processors, Proceedings of the 2001 international symposium on Low power electronics and design, p.28-33, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383089]
• 30: Ranganathan, N., Vijaykrishnan, N., and Bhavanishankar, N. 1998. A linear array processor with dynamic frequency clocking for image processing applications. IEEE Trans. Circ. Syst. Video Techn. 8, 4 (Aug.), 435--445.
• 31: Sarrafzadeh, M. and Raje, S. 1999. Scheduling with multiple voltages under resource constraints. In Proceedings of the IEEE Symposium on Circuits and Systems (Vol. 1). 350--353.
• 32: Shiue, W. T. and Chakrabarti, C. 2000. Low-power scheduling with resources operating at multiple voltages. IEEE Trans. Circ. Syst.-II: Analog Digital Signal Process. 47, 6 (June), 536--543.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Automatic synthesis; Optimization
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Algorithms, Design, Performance, Reliability

Keywords:
High-level synthesis, dynamic frequency clocking, low-power datapath synthesis, multiple voltage scheduling, resource-constrained scheduling, time-constrained scheduling