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Code sharing among states for stack-caching interpreter
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Source Interpreters, Virtual Machines And Emulators archive
Proceedings of the 2004 workshop on Interpreters, virtual machines and emulators table of contents
Washington, D.C.
SESSION: Research papers I table of contents
Pages: 15 - 22  
Year of Publication: 2004
ISBN:1-58113-909-8
Authors
Jinzhan Peng  Intel Corporation
Gansha Wu  Intel Corporation
Guei-Yuan Lueh  Intel Corporation
Sponsors
ACM: Association for Computing Machinery
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
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ABSTRACT

Interpretation has salient merits of simplicity, portability and small footprint but comes with a price of poor performance. Stack caching is a technique to build a high-performance interpreter by keeping source and destination operands of instructions in registers so as to reduce memory accesses involved during interpretation. One drawback of stack caching is that an instruction may have multiple ways to perform interpretation depending on which registers source operands reside in, resulting in code explosion as well as deterioration of code maintainability. This paper presents a code sharing mechanism that achieves performance as efficient as the stack-caching interpreter and in the meantime keeps the code size as compact as general threaded interpreters. Our results show that our approach outperforms a threaded interpreter by an average of 13.6% and the code size increases by only 1KB (~3%).


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Intel Corporation. Intel XScale Microarchitecture for the PXA255 processor: Use's Manual, March 2003.
 
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M. Anton Ertl and David Gregg, The structure and performance of efficient interpreters, in Journal of Instruction-Level Parallelism, vol. 5, November 2003.
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M. Anton Ertl. Implementation of Stack-Based Languages on Register Machines. Dissertation, Technische Universitat Wien, Austria, 1996
 
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Robert Griesemer, Interpreter Generation and Implementation Utilizing Interpreter States and Register Caching, US Patent 6,192,516 B1, Feb. 20, 2001. Filed April 27, 1999. <u>http://www.uspto.gov/</u>
 
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Collaborative Colleagues:
Jinzhan Peng: colleagues
Gansha Wu: colleagues
Guei-Yuan Lueh: colleagues