3D module placement for congestion and power noise reduction

ABSTRACT

3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today's mixed signal system integration. In this work, we propose a 3D module and decap (decoupling capacitance) placement algorithm that simultaneously reduces the power supply noise and wire congestion. We provide efficient algorithms for 3D power supply noise and congestion analysis to guide our 3D module placement process. In addition, we allocate white spaces around the modules that require decaps to suppress the power supply noise while minimizing the area overhead. In our experimentation, we achieve improvements in both decap amount and congestion with only small increase in area, wirelength, and runtime.

REFERENCES

• 1: R. Tummala, "SOP: What is it and why? a new microsystem-integration technology paradigm-moore's law for system integration of miniaturized convergent systems of the next decade," IEEE Transactions on Advanced Packaging, 2004.
• 2: M. Rewienski and J. White, "A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 155--170, 2003.
• 3: A. Kamo, T. Watanabe, and H. Asai, "An optimization method for placement of decoupling capacitors on printed circuit board," in Proc. IEEE Electrical Performance of Electronic Packaging, 2000.
• 4: Y. Chen, Z. Chen, and J. Fang, "Optimum placement of decoupling capacitors on packages and printed circuit boards under the guidance of electromagnetic field simulation," in IEEE Electronic Components and Technology Conference, 1996.
• 5: S. Zhao, C.-K. Koh, and K. Roy, "Decoupling capacitance allocation and its application to power supply noise aware floorplanning," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 81--92, 2002.
• 6: Haihua Su , Sachin S. Sapatnekar , Sani R. Nassif, An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA [doi>10.1145/505388.505405]
• 7: Hung-Ming Chen , Li-Da Huang , I-Min Liu , Minghorng Lai , D. F. Wong, Floorplanning with power supply noise avoidance, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan [doi>10.1145/1119772.1119857]
• 8: Fast Hierarchical Floorplanning with Congestion and Timing Control, Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors, p.357, September 17-20, 2000
• 9: X. Yang, R. Kastner, and M. Sarrafzadeh, "Congestion estimation during top-down placement," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2002.
• 10: M. S. M. Wang, X. Yang, "Congestion minimization during placement," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2000.
• 11: R. Ravichandran, J. Minz, M. Pathak, S. Easwar, and S. K. Lim, "Physical layout automation for system-on-packages," in IEEE Electronic Components and Technology Conference, 2004.
• 12: J. Minz, S. K. Lim, J. Choi, and M. Swaminathan, "Module placement for power supply noise and wire congestion avoidance in 3D packaging," in Proc. IEEE Electrical Performance of Electronic Packaging, 2004.
• 13: J. Minz and S. K. Lim, "A global router for system-on-package targeting layer and crosstalk minimization," in Proc. IEEE Electrical Performance of Electronic Packaging, 2004.
• 14: J. Minz, E. Wong, and S. K. Lim, "Thermal and congestion-aware physical design for 3d system-on-pacakge," in IEEE Electronic Components and Technology Conference, 2005.
• 15: S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by simulated annealing," Science, pp. 671--680, 1983.
• 16: Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani, Rectangle-packing-based module placement, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.472-479, November 05-09, 1995, San Jose, California, United States
• 17: Jacob Minz, Sung Kyu Lim, "A Global Router for System-on-Package Targeting Layer and Crosstalk Minimization,"in IEEE Electrical Performance of Electronic Packaging, 2004.
• 18: Charles J. Alpert, The ISPD98 circuit benchmark suite, Proceedings of the 1998 international symposium on Physical design, p.80-85, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274546]
• 19: N. Na, J. Choi, M. Swaminathan, J. P. Libous, and D. P. O'Connor, "Modeling and simulation of core switching noise for asics," IEEE Trans. Advanced Packaging, pp. 4--11, 2002.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Algorithms, Design

Keywords:
3D module placement, congestion, power noise reduction, system-on-package