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ABSTRACT

This paper reviews the use of skewed monotonic static CMOS logic gates in scaled technologies where gate leakage currents become significant. High-level tradeoffs and synthesis approaches are discussed, and some experiments are constructed to evaluate the gate-level performance tradeoffs in a hypothetical standard 65nm CMOS technology. At the gate level, significant improvements in static power consumption are possible without reduction in evaluation delays, but the tradeoffs vary as the conditions and the amount of skewing are changed. NAND forms are still preferred as the gate leakage grows.

REFERENCES

• 1: http://www-devices.eecs.berkeley.edu/
• 2: http://www.aimspice.com/
• 3: http://www.itrs.net, 2004 International Technology Roadmap for Semiconductors.
• 4: Chulwoo Kim , Ki-Wook Kim , Sung-Mo Kang, Energy-efficient skewed static logic with dual Vt: design and synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.64-70, February 2003 [doi>10.1109/TVLSI.2002.800528]
• 5: Tyler J. Thorp , Gin S. Yee , Carl M. Sechen, Design and synthesis of dynamic circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.141-149, February 2003 [doi>10.1109/TVLSI.2002.800518]
• 6: Phillip Chin , Charles A. Zukowski , George D. Gristede , Stephen Kosonocky, Characterization of logic circuit techniques for high leakage CMOS technologies, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA [doi>10.1145/988952.989008]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design

Keywords:
gate leakage reduction, low power design