Increasing design space of the instruction queue with tag coding

ABSTRACT

The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instructions. This paper proposes decoupling the tags for instruction wakeup from the tags for physical register access, thus increasing the design space of the instruction queue by encoding its operand tags. Two coding methods have been developed. One uses a linear code to increase the Hamming distance between tags, reducing the tag match delay by more than 50% and achieving 12% improvement in the total wakeup/select delay for TSMC 0.18mm technology at 1.8v. The second method uses one-hot code to encode the operand tag, removing the tag OR and tag read operations from the wakeup/select loop. For a 32-entry instruction queue, 15% reduction in the wakeup/select loop has been achieved. Furthermore, one-hot code also removes the dissipation-on-mismatch in the wakeup logic, significantly reducing the dynamic power consumption of the instruction queue.

REFERENCES

• 1: V. Pless, Introduction to the Theory of Error-Correcting Codes, 3rd Edition, Wiley, 1998.
• 2: Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
• 3: Masahiro Goshima , Kengo Nishino , Toshiaki Kitamura , Yasuhiko Nakashima , Shinji Tomita , Shin-ichiro Mori, A high-speed dynamic instruction scheduling scheme for superscalar processors, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
• 4: Energy Efficient Comparators for Superscalar Datapaths, IEEE Transactions on Computers, v.53 n.7, p.892-904, July 2004 [doi>10.1109/TC.2004.29]
• 5: M. S. Hrishikesh , Doug Burger , Norman P. Jouppi , Stephen W. Keckler , Keith I. Farkas , Premkishore Shivakumar, The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays, Proceedings of the 29th annual international symposium on Computer architecture, p.14, May 25-29, 2002, Anchorage, Alaska

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: System architectures

Additional Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.3 Microcomputers
          Subjects: Microprocessors

General Terms:
Design, Experimentation, Performance

Keywords:
instruction queue, wakeup/select loop