Enhancing error resilience for reliable compression of VLSI test data

ABSTRACT

This paper presents a novel methodology to improve error resilience for reliable compression of test data of VLSI circuits. The presence of so-called "bit-flips" (due to the high speed manufacturing test or noise in the Automatic Test Equipment (ATE) head) can lead to a significant loss in coverage when compression is employed. As reported in the technical literature, coverage can experience a reduction of as much as 30% due to bit-flips in the compressed sequence of the test data. Differently from reported works, the proposed technique adds a very small amount of redundant information to test data prior to its compression; the objective of the redundant data is to limit the so-called "propagation" effect due to bit-flips once the sequence is decompressed. Extensive simulation results are presented to substantiate the increase in error resilience and to evaluate the impact of the redundancy introduced by the proposed approach on the compression ratio. It is shown that for the ISCAS89 benchmark circuits the reduction in coverage is only 0.20%-3.52% which is significantly better than previously reported works.

REFERENCES

• 1: Yervant Zorian, Test Requirements for Embedded Core-Based Systems and IEEE P1500, Proceedings of the IEEE International Test Conference, p.191-199, November 03-05, 1997
• 2: Abhijit Jas , Nur A. Touba, Test vector decompression via cyclical scan chains and its application to testing core-based designs, Proceedings of the 1998 IEEE International Test Conference, p.458-464, October 18-22, 1998
• 3: A. Chandra and K. Chakrabarty, "System-on-a-Chip Test-Data Compression and Decompression Architectures Based on Golomb Codes," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 3, pp. 355--368, March 2001.
• 4: Anshuman Chandra , Krishnendu Chakrabarty, Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression, Proceedings of the 19th IEEE VLSI Test Symposium, p.42, March 29-April 03, 2001
• 5: V. Iyengar, K. Chakrabarty, and B. T. Murray, "Huffman Encoding of Test Sets for Sequential Circuits," IEEE Trans. on Instrumentation and Measurement, Vol. 47, No. 1, pp. 21--25, Feb. 1998.
• 6: P. T. Gonciari, B. M. Al-Hashimi, and N. Nicolici "Variable-Length Input Huffman Coding for System-on-a-Chip Test," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 6, pp. 783--796, June 2003.
• 7: A. Jas, J. G. Dastidar, N. M. Eng, and N. A. Touba, "An Efficient Test Vector Compression Scheme Using Selective Huffman Coding," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 6, pp. 797--806, June 2003.
• 8: H. Hashempour , L. Schiano , F. Lombardi, Error-Resilient Test Data Compression Using Tunstall Codes, Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium on (DFT'04), p.316-323, October 10-13, 2004
• 9: B. P. Tunstall, "Synthesis of Noiseless Compression Codes," Ph. D. thesis, Georgia Institute of Technology, 1967.
• 10: Hamidreza Hashempour , Luca Schiano , Fabrizio Lombardi, Evaluation of Error-Resilience for Reliable Compression of Test Data, Proceedings of the conference on Design, Automation and Test in Europe, p.1284-1289, March 07-11, 2005 [doi>10.1109/DATE.2005.142]
• 11: B. West, "Private Communication," NPTest.
• 12: Ilker Hamzaoglu , Janak H. Patel, Test set compaction algorithms for combinational circuits, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.283-289, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288615]
• 13: K. Helsgaun, "An Effective Implementation of the Lin-Kernighan Traveling Salesman Heuristic," European Journal of Operational Research, Vol. 126, No. 1, pp. 106--130, 2000.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Reliability

Keywords:
ATE, reliable compression, test data compression