| A sensitivity analysis of low-power repeater insertion |
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Great Lakes Symposium on VLSI
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Proceedings of the 15th ACM Great Lakes symposium on VLSI
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Chicago, Illinois, USA
SESSION: High-level low power design I
table of contents
Pages: 244 - 247
Year of Publication: 2005
ISBN:1-59593-057-4
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Authors
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Yuantao Peng
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North Carolina State University, Raleigh, NC
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Xun Liu
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North Carolina State University, Raleigh, NC
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Downloads (6 Weeks): 1, Downloads (12 Months): 24, Citation Count: 0
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ABSTRACT
In this paper, we perform the first quantitative study on the sensitivities of repeater power to available repeater width and candidate location, two key parameters of the dynamic programming (DP) based repeater insertion algorithms. Based on our analysis, we propose a simple yet effective scheme to select repeater widths and locations for DP-based algorithms, achieving an excellent trade-off between the solution quality and runtime. Experimental results have shown that, when combined with our sensitivity-guided scheme, the DP algorithm can attain more than 6 times speedup with negligible power degradation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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