Energy optimization in memory address bus structure for application-specific systems

ABSTRACT

Energy optimization for high-capacitance on-chip buses has become a critical problem in VLSI design, especially for embedded or SoC systems. Coupling effects between bus wires make this issue even more urgent. Coding schemes have been proposed to reduce the energy dissipation. However, the circuits overhead increases significantly when the coding schemes consider the inter-wire capacitances. In this paper, we present a novel method for energy optimization in memory address bus (MAB). The data on application specified MAB has different characters to the data bus, which has high repetition vectors and unevenly distributed switch activity. Thus a combined method is proposed to optimize the energy consumption by both self capacitance and inter-wire capacitance. First, we lower the switch activity by an efficient coding scheme. Based on the statistical data, a modified bus-invert coding scheme can intelligently divide bus lines into groups and apply bus-invert coding. It brings ultra-low area or timing penalty because of the simple circuit structure. Then the energy consumption of coupling capacitances is optimized by net reordering technique. Implemented with table-look-up technique, a fast simulated annealing algorithm is proposed to solve the net reordering problem. The experimental results show that our combined method is very efficient to reduce the energy consumption in memory address bus for varieties of applications.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design, Performance