Two dimensional reordering of functional test data for compression by ATE

ABSTRACT

This paper presents a novel approach for compressing functional test data in Automatic Test Equipment (ATE). A practical technique is presented for 2 Dimensional (2D) reordering of test data in which additionally to test vector reordering, column reordering is also applied. An ATE based approach to extract the original test vectors from the 2D ordered data is presented. The advantage of the approach is substantiated using the figure of merit of entropy for the 2D ordered test data of ISCAS benchmark circuits.

REFERENCES

• 1: Yervant Zorian, Test Requirements for Embedded Core-Based Systems and IEEE P1500, Proceedings of the IEEE International Test Conference, p.191-199, November 03-05, 1997
• 2: Irith Pomeranz , Lakshmi N. Reddy , Sudhakar M. Reddy, COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.194-203, October 26-30, 1991
• 3: J.-S. Chang and C.-S. Lin, "Test Set Compaction for Combinational Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, pp. 1370--1378, Nov. 1995.
• 4: I. Hamzaoglu and J. H. Patel, "Test Set Compaction Algorithms for Combinational Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 8, pp. 957--963, Aug. 2000.
• 5: Aiman El-Maleh , Esam Khan , Saif al Zahir, A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip, Proceedings of the 19th IEEE VLSI Test Symposium, p.54, March 29-April 03, 2001
• 6: Takahiro Yamaguchi , Masahiro Ishida , Marco Tilgner , Dong Sam Ha, An Efficient Method for Compressing Test Data, Proceedings of the IEEE International Test Conference, p.79-88, November 03-05, 1997
• 7: Abhijit Jas , Nur A. Touba, Test vector decompression via cyclical scan chains and its application to testing core-based designs, Proceedings of the 1998 IEEE International Test Conference, p.458-464, October 18-22, 1998
• 8: A. Chandra and K. Chakrabarty, "System-on-a-chip test-data compression and decompression architectures based on Golomb codes," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 3, pp. 355--368, March 2001.
• 9: P. T. Gonciari, B. M. Al-Hashimi and N. Nicolici "Variable-Length Input Huffman Coding for System-on-a-Chip Test," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 6, pp. 783--796, June 2003.
• 10: A. Jas, J. G. Dastidar, N. M. Eng and N. A. Touba, "An efficient test vector compression scheme using selective Huffman coding," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 6, pp. 797--806, June 2003.
• 11: F. Karimi, Z. Navabi, W. M. Meleis and F. Lombardi, "Using Data Compression in Automatic Test Equipment for System-on-Chip Testing," IEEE Trans. on Instrumentation and Measurement, Vol. 53, No. 2, pp. 308--317, April 2004.
• 12: Hamidreza Hashempour , Fabrizio Lombardi, ATE-Amenable Test Data Compression with No Cyclic Scan, Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, p.151, November 03-05, 2003
• 13: Timothy Alton, TGEN: Flexible Timing Generator Architecture, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.439-443, September 20-24, 1992
• 14: M. L. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits," Kluwer Academic Pub., 2000.
• 15: K. Helsgaun, "An Effective Implementation of the Lin-Kernighan Traveling Salesman Heuristic," European Journal of Operational Research 126 (1), 106--130 (2000).

INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING

General Terms:
Algorithms

Keywords:
2D reordering, ATE, column reordering, functional test data, scan test data, test data compression