Digital cell macro-model with regular substrate template and EKV based MOSFET model

ABSTRACT

This paper presents substrate noise macro-models for standard digital cells, like INV, NAND and BUFFER. The macro-models are based on a scalable substrate network template and a compact MOSFET model equivalent to EKV model. Our models and simulator predicted the substrate voltage, injection currents, and output voltage of each primary digital cell. Proposed models are close to device physics and valid for different processing technology and input transition. They are more accurate as compared to macro-models generated from curve fitting. Our macro-model accuracy is within 5-10% from SPICE simulation with MOSFET level49 models, and at least 4 times faster. This model can be used to predict spatially and temporally the occurrence of substrate noise peaks in a digital design.

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