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Area-efficient two-dimensional architectures for finite field inversion and division
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 15th ACM Great Lakes symposium on VLSI table of contents
Chicago, Illinois, USA
POSTER SESSION: Poster session 1 table of contents
Pages: 116 - 121  
Year of Publication: 2005
ISBN:1-59593-057-4
Authors
Zhiyuan Yan  Lehigh University, Bethlehem, PA
Dilip V. Sarwate  University of Illinois at Urbana-Champaign, Urbana, IL
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

Many high-throughput two-dimensional architectures for finite field inversion and division are based on reformulations of the extended Euclidean algorithm (EEA). These reformulated EEAs usually keep track of two pairs of data polynomials (or registers), and the operations of the reformulated EEAs are only within each pair of polynomials. In this paper, we propose a new reformulated EEA wherein the operations within the two pairs of polynomials are identical. Hence, the two pairs of polynomials in our new reformulated EEA can be concatenated into one pair. By utilizing some inherent properties of the EEA, we further reduce the computational complexity of our reformulated EEA by 25%. Based on our reformulated EEA, we propose new two-dimensional inversion and division architectures. How much hardware saving the reduced computational complexity translates into depends on how control mechanisms are implemented. Regardless of the implementation of control signals, our new architectures require smaller numbers of gates and latches while achieving comparable or better throughput, latency, and critical path delay in comparison to the best architectures in the literature.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
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Collaborative Colleagues:
Zhiyuan Yan: colleagues
Dilip V. Sarwate: colleagues