Integer linear programming based energy optimization for banked DRAMs

ABSTRACT

Memory system can be a major energy consumer in an embedded architecture. One way of reducing its energy consumption is banking, i.e., dividing available memory space into multiple, equally sized banks and placing an unused (idle) memory bank into a low-power operating mode. Prior work investigated code restructuring and data layout reorganization based approaches for increasing energy benefits that could be obtained from a banked memory architecture. This paper takes a different look at the problem of energy optimization in banked memory systems, and explores two compiler-assisted techniques that can co-exist with code/data transformations: data migration and data compression. The goal of data migration is to cluster data with similar access patterns in the same set of banks, thereby increasing the chances for utilizing low-power operating modes in a more effective manner. Data compression reduces the size of the data used by the application, and thus helps reduce the number of memory banks occupied by data. This in turn allows us place a larger number of banks into the low-power operating modes. We formulate the memory bank management problem as an ILP (integer linear programming) problem, and solve it using a publicly available ILP package.

REFERENCES

• 1: 128/144-MBit Direct RDRAM Data Sheet, Rambus Inc., 1999.
• 2: Navid Azizi , Farid N. Najm , Andreas Moshovos, Low-leakage asymmetric-cell SRAM, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.701-715, August 2003 [doi>10.1109/TVLSI.2003.816139]
• 3: Francky Catthoor , Eddy de Greef , Sven Suytack, Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design, Kluwer Academic Publishers, Norwell, MA, 1998
• 4: Yun Cao , Hiroyuki Tomiyama , Takanori Okuma , Hiroto Yasuura, Data memory design considering effective bitwidth for low-energy embedded systems, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan [doi>10.1145/581199.581245]
• 5: V. Delaluz et al., "Improving off-chip memory energy behavior in a multi-processor, multi-bank environment," In Proc. the 14th LCPC, 2001.
• 6: and M. J. Irwin, DRAM Energy Management Using Sof ware and Hardware Directed Power Mode Control, Proceedings of the 7th International Symposium on High-Performance Computer Architecture, p.159, January 20-24, 2001
• 7: Keith I. Farkas , Jason Flinn , Godmar Back , Dirk Grunwald , Jennifer M. Anderson, Quantifying the energy consumption of a pocket computer and a Java virtual machine, Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, p.252-263, June 18-21, 2000, Santa Clara, California, United States
• 8: Mahmut T. Kandemir , Ibrahim Kolcu , Ismail Kadayif, Influence of Loop Optimizations on Energy Consumption of Multi-bank Memory Systems, Proceedings of the 11th International Conference on Compiler Construction, p.276-292, April 08-12, 2002
• 9: Alvin R. Lebeck , Xiaobo Fan , Heng Zeng , Carla Ellis, Power aware page allocation, Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, p.105-116, November 2000, Cambridge, Massachusetts, United States
• 10: lp solve. ftp://ftp.es.ele.tue.nl/pub/lp solve/
• 11: J. Moon et al., "Low-power sequential access memory design," In Proc. the IEEE Custom Integrated Circuits Conference, 2002.
• 12: George L. Nemhauser , Laurence A. Wolsey, Integer and combinatorial optimization, Wiley-Interscience, New York, NY, 1988
• 13: Preeti Ranjan Panda, Memory bank customization and assignment in behavioral synthesis, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.477-481, November 07-11, 1999, San Jose, California, United States
• 14: Mazen A. R. Saghir , Paul Chow , Corinna G. Lee, Exploiting dual data-memory banks in digital signal processors, Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, p.234-243, October 01-04, 1996, Cambridge, Massachusetts, United States
• 15: www.virtutech.com/products/simics.html
• 16: Ashok Sudarsanam , Sharad Malik, Simultaneous reference allocation in code generation for dual data memory bank ASIPs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.242-264, April 2000 [doi>10.1145/335043.335047]
• 17: Robert P. Wilson , Robert S. French , Christopher S. Wilson , Saman P. Amarasinghe , Jennifer M. Anderson , Steve W. K. Tjiang , Shih-Wei Liao , Chau-Wen Tseng , Mary W. Hall , Monica S. Lam , John L. Hennessy, SUIF: an infrastructure for research on parallelizing and optimizing compilers, ACM SIGPLAN Notices, v.29 n.12, p.31-37, Dec. 1994 [doi>10.1145/193209.193217]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.0 General

General Terms:
Design

Keywords:
DRAM, ILP, data compression, data migration, low-power, memory banking