High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping

ABSTRACT

We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability, even in presence of clustered faults, a fault pattern for which previous BIST methods proved ineffective. Unlike previous BIST methods which unrealistically assume that the test circuitry used for testing PLBs is fault-free, our method, via an iterative bootstrapping process, first finds this fault-free test circuitry and then starts testing the PLBs. Also, unlike previous methods, our fault detection process does not require any unrealistic assumptions of fault-free status of some components or the existence of only some fault patterns (and the exclusion of others) in the FPGA. Our adaptive fault diagnosis process is more time efficient than its previous counterparts as it does not require testing of all the PLBs of a faulty BIST area, and its design is simpler in the sense that it does not require multiple modifications of the testing area for its implementation. We also analyze the probability of correct diagnosis in the presence of multiple faults. Our BIST technique gives excellent fault coverage and fault latency results, and supports the theoretical analysis.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.0 General

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Algorithms, Design, Reliability

Keywords:
FPGAs, built-in self-tester (BISTer), diagnosability, functional testing, on-line testing, roving tester (ROTE)