Characterizing the VCO jitter due to the digital simultaneous switching noise

ABSTRACT

We study the simultaneous switching noise(SSN) generated by the digital I/O buffers and its impact on VCO. A simple yet accurate model is developed to analyze the ground bounce and power supply fluctuation in each region respectively. Calculation results with the models show good agreements with HSPICE simulation results. Based on the noise model, we investigate the SSN effects on the timing jitter of a current starved VCO. In this study, the RMS jitter and jittery signal spectrum are characterized.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Design, Measurement, Reliability

Keywords:
VCO, buffer, jitter, simultaneous switching noise