ACM Home Page
Please provide us with feedback. Feedback
PIM lite: a multithreaded processor-in-memory prototype
Full text PdfPdf (272 KB)
Source Great Lakes Symposium on VLSI archive
Proceedings of the 15th ACM Great Lakes symposium on VLSI table of contents
Chicago, Illinois, USA
SESSION: Computer architecture table of contents
Pages: 64 - 69  
Year of Publication: 2005
ISBN:1-59593-057-4
Authors
Shyamkumar Thoziyoor  University of Notre Dame
Jay Brockman  University of Notre Dame
Daniel Rinzler  Harvey Mudd College
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 32,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1057661.1057678
What is a DOI?

ABSTRACT

PIM Lite is a processor-in-memory prototype implemented in a 0.18 micron logic process. PIM Lite provides a complete working demonstration of a minimal-state, lightweight multithreaded processor with low-overhead thread swapping. Minimizing processor state by keeping thread state in memory and using a regular, tiled and memory-centric design greatly simplified VLSI development and testing.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
C. Kozyrakis et al. Vector IRAM: A media-enhanced vector processor with embedded DRAM. In Hot Chips, 2000.
2
 
3
4
5
 
6
J. Brockman. PIM Lite architecture and assembly language manual. Technical report, University of Notre Dame CSE Dept., 2003.
 
7
J. Brockman. Programming PIM Lite. Technical report, University of Notre Dame CSE Dept., 2003.
8
 
9
Shyamkumar Thoziyoor. PIM Lite: VLSI prototype of a multithreaded processor-in-memory chip. M.S. thesis, University of Notre Dame, 2004.
 
10
 
11
L. Pileggi et al. Exploring regular fabrics to optimize the performance-cost trade-off. In DAC, 2000.
 
12
One Hot Logic LLC. http://www.onehotlogic.com.

Collaborative Colleagues:
Shyamkumar Thoziyoor: colleagues
Jay Brockman: colleagues
Daniel Rinzler: colleagues