Thermal aware cell-based full-chip electromigration reliability analysis

ABSTRACT

A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-based electromigration analysis suitable for integrating electromigration reliability analysis into a conventional IC design flow. A block or cell is characterized for reliability while it is characterized for power and timing. Reusing cell characterization data significantly reduces computational load while analyzing a full-chip layout. During full-chip analysis, we compute a layout-level temperature profile from cell power dissipations using a Fast Fourier Transform based algorithm. The described full-chip reliability assessment methodology has been implemented in an interconnect reliability CAD tool. We have exercised the tool to demonstrate performance-reliability tradeoff and the significance of thermal-aware reliability analysis for true reliability aware design.

REFERENCES

• 1: International Technology Roadmap for Semiconductors (ITRS), http://public.itrs.net/.
• 2: C-C Teng et al., "iTEM: A Temperature-Dependent Electromigration Reliability Diagnosis Tool," IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 16, no 8, August 1997.
• 3: C. V. Thompson et al., "Modeling and Experimental Characterization of Electromigration in Interconnect Trees," in Proceedings of Workshop on Stress Induced Phenomena in Metallization, pp. 62--73, 1999.
• 4: C. V. Thompson et al., "Experiments and Models for Circuit-Level Assessment of the Reliability of Cu Metallization," in Proceedings of IITC, p 69, 2004.
• 5: M. J. Dion, "Electromigration lifetime enhancement for lines with multiple branches," in Proceedings of the International Reliability Physics Symposium, pp. 324--332, 2000.
• 6: Syed M. Alam , Gan Chee Lip , Carl V. Thompson , Donald E. Troxel, Circuit Level Reliability Analysis of Cu Interconnects, Proceedings of the 5th International Symposium on Quality Electronic Design, p.238-243, March 22-24, 2004
• 7: I. A. Blech, J. Appl. Phys. vol 47, p 1203 (1976).
• 8: R. G. Filippi et al, App. Phys. Lett. 69, 2350 (1996).
• 9: Johannes Grad , James E. Stine, A Standard Cell Library for Student Projects, Proceedings of the 2003 International Conference on Microelectronics Systems Education, p.98, June 01-02, 2003
• 10: J. R. Black, in Proceedings of the International Reliability Physics Symposium, p.148, 1995.
• 11: M. B. Kleiner et al., "Thermal Analysis of Vertically Integrated Circuits," in Proc. IEDM, p487, 1995.
• 12: K. Jenkins and R. L. Franch, "Impact of Self-Heating on Digital SOI and Strained-Silicon CMOS Circuits," in Proc. SOI Conf. p161, 2003.
• 13: J. Behm and J. Huttunen, "Heat Spreading and Conduction in Compressed Heatsink," in Proc. of the International Flotherm Users Conference, 2001.
• 14: Ting Yen Chiang , Kaustav Banerjee , Krishna C. Saraswat, Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 15: L. T. Su et al., "Measurement and modeling of self-heating in SOI nMOSFET's," IEEE TED, vol. 41, pp 69--75, 1994.
• 16: G. G. Shahidi, "SOI Technology in the GHz Era," IBM Journal of R&D, vol. 46, pp. 121--131, 2002.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.0 General

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Design, Performance, Reliability

Keywords:
IC thermal analysis, electromigration, full-chip reliability, reliability aware design, reliability characterization