Physical limitations on the bit-rate of on-chip interconnects

ABSTRACT

It is shown in this paper that contrary to the common conception, widening an on-chip interconnect wire will not cause the wire to behave as a lossless line. It is shown that the energy losses actually increase when widening a wire. The damping factor of the line, which determines the maximum bit rate that can be transmitted on a wire, also does not go to zero for wide wires as in lossless lines. This fact results in a serious physical limitation on the maximum bit rate that can be transmitted on a wire. It is shown that by increasing the cross-sectional width of an interconnect wire, the damping factor will saturate to a certain limit. An expression for this minimum damping factor for very wide wires is derived from fundamental physical constants and used to introduce an expression for the maximum bit rate that can be reached by widening an interconnect wire for a certain technology. It is shown that for current technology numbers, the maximum bit rate on a wire can be quite limiting for longer wires and that scaling trends will even decrease more this maximum bit rate, posing a serious limitation.

REFERENCES

• 1: J. D. Meindl, J. A. Davis, P. Zarkesh-Ha, C. S. Patel, K. P. Marti,P. A. Kohl "Interconnect opportunities for gigascale integration" IBM J. RES. & DEV. Vol. 46 No. 2/3 March/May 2002.
• 2: H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990. Technology Conf. Proc., 1999, pp. 24--26.
• 3: G. Sai-Halz, "Performance trends in high-end processors," Proc.IEEE, vol. 83, pp. 20--36, Jan. 1995.
• 4: Yehea I. Ismail , Eby G. Friedman, Effects of inductance on the propagation delay and repeater insertion in VLSI circuits, Proceedings of the 36th ACM/IEEE conference on Design automation, p.721-724, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310042]
• 5: "ELDO User's manual", Mentor Graphics Corporation 2002.
• 6: "FastHenry User's guide", Massachusett's Institute of Technology, Cambridge.
• 7: "FastCap User's guide", Massachusett's Institute of Technology, Cambridge.
• 8: J.D.Jackson,"Classical electrodynamics" John Wiley & Sons, Inc., New York, USA,1962, pp. 199, 1st edition.
• 9: S. Powell, W.R. Smith, and G. Persky, "A parasitic extraction program for closely-spaced VLSI interconnects," Proceeding of IEEE International Conference CAD, 1985, pp. 193--195.
• 10: Erich Brake, "Line-to-ground capacitance calculation for VLSI: A comparison," IEEE Transactions on Computer-Aided Design, vol. 7, No. 2, February 1998.
• 11: M. Sgroi , M. Sheets , A. Mihal , K. Keutzer , S. Malik , J. Rabaey , A. Sangiovanni-Vencentelli, Addressing the system-on-a-chip interconnect woes through communication-based design, Proceedings of the 38th conference on Design automation, p.667-672, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379045]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)

General Terms:
Design, Performance, Theory

Keywords:
bit-rate, damping factor, delay, interconnects