Low power test generation for path delay faults using stability functions

ABSTRACT

A recent work describes an ATPG for path delay faults that limits the power dissipated by the test patterns to a given bound. However, the power dissipated by the intermediate patterns while applying the test patterns in a sequence is not considered. Experiments with test patterns derived from different ATPGs has shown that the switching activity due to intermediate patterns dissipate considerable power. This paper proposes a method to incorporate stability functions in a functional ATPG to derive test vectors that guarantee reduced power dissipation by the intermediate patterns without loss in PDF coverage.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Algorithms, Performance, Verification

Keywords:
ATPG, low power, path delay faults