|
ABSTRACT
It is a common belief that computer performance growth is over 50% annually, or that performance doubles every 18-20 months. By analyzing publicly available results from the SPEC integer (CINT) benchmark suites, we conclude that this was true between 1985 and 1996 -- the early years of the RISC paradigm.During the last 7.5 years (1996-2004), however, performance growth has slowed down to 41%, with signs of a continuing decline. Meanwhile, clock frequency has improved with about 29% annually. The improvement in clock frequency was enabled both by an annual device speed scaling of 20% as well as by longer pipelines with a lower gate-depth in each stage. This paper takes a fresh look at -- and tries to remove the confusion about -- performance scaling that exists in the computer architecture community.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
Vikas Agarwal , M. S. Hrishikesh , Stephen W. Keckler , Doug Burger, Clock rate versus IPC: the end of the road for conventional microarchitectures, Proceedings of the 27th annual international symposium on Computer architecture, p.248-259, June 2000, Vancouver, British Columbia, Canada
|
 |
2
|
|
| |
3
|
Paul E. Gronowski, William J. Bowhill, Ronald P. Preston, Michael K. Gowan and Randy L. Allmon, High-Performance Microprocessor Design, Journal of Solid-State Circuits, vol. 33, 676--686, 1998.
|
| |
4
|
|
| |
5
|
|
| |
6
|
|
| |
7
|
|
| |
8
|
I. Tuimi, The Lives and Death of Moore's Law, First Monday, Oct 11, 2002.
|
CITED BY 2
|
|
|
|
|
Brent Cowan , Bill Kapralos, Spatial sound for video games and virtual environments utilizing real-time GPU-based convolution, Proceedings of the 2008 Conference on Future Play: Research, Play, Share, November 03-05, 2008, Toronto, Ontario, Canada
|
|