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Capo: robust and scalable open-source min-cut floorplacer

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International Symposium on Physical Design archive
Proceedings of the 2005 international symposium on Physical design table of contents

San Francisco, California, USA

SESSION: 2005 ISPD placement contest table of contents

Pages: 224 - 226

Year of Publication: 2005

ISBN:1-59593-021-3

Authors

Jarrod A. Roy	University of Michigan, Ann Arbor, MI
David A. Papa	University of Michigan, Ann Arbor, MI
Saurabh N. Adya	Synplicity Inc., Sunnyvale, CA
Hayward H. Chan	University of Michigan, Ann Arbor, MI
Aaron N. Ng	University of Michigan, Ann Arbor, MI
James F. Lu	University of Michigan, Ann Arbor, MI
Igor L. Markov	University of Michigan, Ann Arbor, MI

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 39, Citation Count: 16

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

In this invited note we describe Capo, an open-source software tool for cell placement, mixed-size placement and floorplanning with emphasis on routability. Capo is among the fastest academic placers and scales to millions of movable objects. This note surveys the overall structure of Capo, discusses recent improvements and describes ongoing research.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Saurabh N. Adya , Igor L. Markov , Paul G. Villarrubia, On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.311, November 09-13, 2003 [doi>10.1109/ICCAD.2003.107]
	2	S. N. Adya et al., "Benchmarking for Large-Scale Placement and Beyond," IEEE Trans. on CAD 23(4), pp. 472--488, 2004.
	3	S. N. Adya , S. Chaturvedi , J. A. Roy , D. A. Papa , I. L. Markov, Unification of partitioning, placement and floorplanning, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.550-557, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382639]
	4	S. N. Adya , I. L. Markov, Combinatorial techniques for mixed-size placement, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.58-90, January 2005 [doi>10.1145/1044111.1044116]
	5	Ameya Agnihotri , Mehmet Can YILDIZ , Ateen Khatkhate , Ajita Mathur , Satoshi Ono , Patrick H. Madden, Fractional Cut: Improved Recursive Bisection Placement, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.307, November 09-13, 2003 [doi>10.1109/ICCAD.2003.72]
	6	Charles J. Alpert , Gi-Joon Nam , Paul G. Villarrubia, Free space management for cut-based placement, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.746-751, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774682]
	7	U. Brenner , J. Vygen, Faster optimal single-row placement with fixed ordering, Proceedings of the conference on Design, automation and test in Europe, p.117-121, March 27-30, 2000, Paris, France [doi>10.1145/343647.343716]
	8	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Design and implementation of move-based heuristics for VLSI hypergraph partitioning, Journal of Experimental Algorithmics (JEA), 5, p.5-es, 2000 [doi>10.1145/351827.384247]
	9	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Improved algorithms for hypergraph bipartitioning, Proceedings of the 2000 conference on Asia South Pacific design automation, p.661-666, January 2000, Yokohama, Japan [doi>10.1145/368434.368864]
	10	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Can recursive bisection alone produce routable placements?, Proceedings of the 37th conference on Design automation, p.477-482, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337549]
	11	A. E. Caldwell, A. B. Kahng, I. L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout," IEEE Trans. on CAD 19(11), pp. 1304--1314, 2000.
	12	Andrew E. Caldwell , Igor L. Markov, Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms, IEEE Design & Test, v.19 n.3, p.72-81, May 2002
	13	A. E. Caldwell, A. B. Kahng, I. L. Markov, "Hierarchical Whitespace Allocation in Top-down Placement," IEEE Transactions on CAD 22(11), Nov, 2003, pp. 716--724.
	14	Andrew B. Kahng , Sherief Reda, Placement feedback: a concept and method for better min-cut placements, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996670]
	15	David A. Papa , Saurabh N. Adya , Igor L. Markov, Constructive benchmarking for placement, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA [doi>10.1145/988952.988981]
	16	N. Selvakkumaran and G. Karypis, "THETO: A Fast and High-Quality Partitioning Driven Global Placer," Technical Report 03-046, 2003, University of Minnesota.
	17	Xiaoping Tang , Ruiqi Tian , Martin D. F. Wong, Optimal redistribution of white space for wire length minimization, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120900]
	18	Xiaojian Yang , Bo-Kyung Choi , Majid Sarrafzadeh, Routability driven white space allocation for fixed-die standard-cell placement, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA [doi>10.1145/505388.505400]

CITED BY 16

	Andrew B. Kahng , Sherief Reda, A tale of two nets: studies of wirelength progression in physical design, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Jason Cong , Kirill Minkovich, Optimality study of logic synthesis for LUT-based FPGAs, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Sherief Reda , Amit Chowdhary, Effective linear programming based placement methods, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Aaron N. Ng , Igor L. Markov , Rajat Aggarwal , Venky Ramachandran, Solving hard instances of floorplacement, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Michael D. Moffitt , Aaron N. Ng , Igor L. Markov , Martha E. Pollack, Constraint-driven floorplan repair, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Zhong Xiu , Rob A. Rutenbar, Mixed-size placement with fixed macrocells using grid-warping, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Peter Spindler , Ulf Schlichtmann , Frank M. Johannes, Abacus: fast legalization of standard cell circuits with minimal movement, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Jianhua Li , Laleh Behjat , Jie Huang, An effective clustering algorithm for mixed-size placement, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Peter Spindler , Frank M. Johannes, Fast and robust quadratic placement combined with an exact linear net model, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	A. B. Kahng , S. Reda , Qinke Wang, Architecture and details of a high quality, large-scale analytical placer, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.891-898, November 06-10, 2005, San Jose, CA
	K. Vorwerk , A. Kennings, Mixed-size placement via line search, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.899-904, November 06-10, 2005, San Jose, CA
	Aswin Sreedhar , Alodeep Sanyal , Sandip Kundu, On modeling and testing of lithography related open faults in nano-CMOS circuits, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Jarrod A. Roy , Aaron N. Ng , Rajat Aggarwal , Venky Ramachandran , Igor L. Markov, Solving modern mixed-size placement instances, Integration, the VLSI Journal, v.42 n.2, p.262-275, February, 2009
	Fan Mo , Robert K. Brayton, Placement based multiplier rewiring for cell-based designs, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Ali Jahanian , Morteza Saheb Zamani, Improved performance and yield with chip master planning design methodology, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
	Yaoguang Wei , Sheqin Dong , Xianlong Hong, APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement, Integration, the VLSI Journal, v.40 n.4, p.406-419, July, 2007