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FastPlace: an analytical placer for mixed-mode designs
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Source International Symposium on Physical Design archive
Proceedings of the 2005 international symposium on Physical design table of contents
San Francisco, California, USA
SESSION: 2005 ISPD placement contest table of contents
Pages: 221 - 223  
Year of Publication: 2005
ISBN:1-59593-021-3
Authors
Natarajan Viswanathan  Iowa State University, Ames, IA
Min Pan  Iowa State University, Ames, IA
Chris Chong-Nuen Chu  Iowa State University, Ames, IA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 8,   Downloads (12 Months): 30,   Citation Count: 4
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ABSTRACT

Modern designs often contain a combination of a large number of standard cells and macro blocks. Traditionally large macro blocks are handled at the floorplanning level, after which their positions are fixed. The standard cells are then handled during the placement level. Current designs can have hundreds of large and medium sized macro blocks and a large number of standard cells. As a result, traditional floorplanning techniques cannot scale to this problem, both in terms of runtime and solution quality. Hence a technique is required to simultaneously handle this combination of placeable objects.In this paper, we present a combined placement and floorplanning approach for mixed-mode placement. We extend the efficient analytical placement algorithm FastPlace by integrating a simulated annealing based floorplanner to solve the global placement problem for mixed-mode designs. We also present an efficient and effective detailed placement algorithm to improve the wirelength of the global placement solution based on a greedy swapping heuristic.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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The International Technology Roadmap for Semiconductors. Semiconductor Industry Association, 2004.
 
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S. Goto. An efficient algorithm for the two-dimensional placement problem in electrical circuit layout. IEEE Trans. on Circuits and Systems, Vol. CAS-28(1):12--18, 1981.
 
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G. Karypis. Multilevel Optimization in VLSICAD. Kluwer Academic Publishers, 2003.
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N. Viswanathan and C. C.-N. Chu. Fastplace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. IEEE Trans. Computer-Aided Design, to appear, 2005.
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Collaborative Colleagues:
Natarajan Viswanathan: colleagues
Min Pan: colleagues
Chris Chong-Nuen Chu: colleagues