Multi-bend bus driven floorplanning

ABSTRACT

In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and the bus specification (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through its blocks, with the area of the floorplan and the total area of the buses minimized. The approach proposed is based on a Simulated Annealing framework. Using the sequence pair representation, we derived the necessary conditions for feasible buses, for which we allow 0-bend, one-bend, or two-bend. Then, we will check whether there are buses that cannot be placed at the same time. Finally, a solution will be generated giving the coordinates of the modules and the buses. Comparing with the results of the algorithm by Xiang et al., the dead space of the floorplan obtained is reduced. Besides, our algorithm can handle buses going through many blocks. For example, if the buses have to go through more than 10 blocks, is not able to generate any solution while our algorithm can still generate solutions of good quality.

REFERENCES

• 1: Evangeline F. Y. Young , M. L. Ho , Chris C. N. Chu, A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.661, January 07-11, 2002
• 2: Yuchun Ma , Xianlong Hong , Sheqin Dong , Yici Cai , Chung-Kuan Cheng , Jun Gu, Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list, Proceedings of the 38th conference on Design automation, p.770-775, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379063]
• 3: Xiaoping Tang , D. F. Wong, FAST-SP: a fast algorithm for block placement based on sequence pair, Proceedings of the 2001 conference on Asia South Pacific design automation, p.521-526, January 2001, Yokohama, Japan [doi>10.1145/370155.370523]
• 4: Xiaoping Tang , D. F. Wong, Floorplanning with alignment and performance constraints, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514128]
• 5: Hua Xiang , Xiaoping Tang , Martin D. F. Wong, Bus-Driven Floorplanning, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.66, November 09-13, 2003 [doi>10.1109/ICCAD.2003.43]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Algorithms, Design

Keywords:
VLSI CAD, bus planning, floorplanning