Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation

ABSTRACT

This paper studies the impacts of Chemical Mechanical Polishing (CMP)-induced systematic variation and random channel length (Leff) variation of transistors on interconnect design. We first construct a table look-up based interconnect RC parasitic model considering CMP effects with optimized fill insertion. Based on the model, we solve the simultaneous buffer insertion, wire sizing and fill insertion (SBWF) problem under CMP variation. We also extend the SBWF problem to consider the random Leff variation (SBWF). We approach the resulting vSBWF problem by (1) incorporating probability density function (PDF) into the SBWF algorithm; and (2) developing an efficient heuristic for PDF pruning, whose practical optimality is verified by an accurate but much slower pruning. Experimental results show that the SBWF design improves timing by 1.0% and reduces power by 5.7% on average with 7.4% less buffer area over the conventional buffer insertion and wire sizing design followed by fill insertion (SBWF), and that the vSBWF design reduces yield loss due to CMP and Leff variations by 44.3% on average over the SBWF design. The runtime of vSBWF is 8.3x that of SBWF, and vSBWF for the largest example containing 3103 sinks finishes in 124 minutes.

REFERENCES

• 1: Chandu Visweswariah, Death, taxes and failing chips, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775921]
• 2: Yu Chen , Puneet Gupta , Andrew B. Kahng, Performance-impact limited area fill synthesis, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775841]
• 3: T. Tugbawa, T. Park, D. Boning, T. Pan, P. Li, S. Hymes, T. Brown, and L. Camilletti, "A mathematical model of pattern dependencies in cu cmp processes," in CMP Symposium, Electrochemical Society Meeting, Oct 1999.
• 4: Puneet Gupta , Fook-Luen Heng, Toward a systematic-variation aware timing methodology, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996660]
• 5: J. A. G. Jess , K. Kalafala , S. R. Naidu , R. H. J. M. Otten , C. Visweswariah, Statistical timing for parametric yield prediction of digital integrated circuits, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.776066]
• 6: Aseem Agarwal , David Blaauw , Vladimir Zolotov , Sarma Vrudhula, Computation and Refinement of Statistical Bounds on Circuit Delay, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775922]
• 7: C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996663]
• 8: Vishal Khandelwal , Azadeh Davoodi , Akash Nanavati , Ankur Srivastava, A Probabilistic Approach to Buffer Insertion, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.560, November 09-13, 2003 [doi>10.1109/ICCAD.2003.16]
• 9: L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. IEEE Int. Symp. on Circuits and Systems, pp. 865--868, 1990.
• 10: Anirudh Devgan , Chandramouli Kashyap, Block-based Static Timing Analysis with Uncertainty, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.607, November 09-13, 2003 [doi>10.1109/ICCAD.2003.41]
• 11: Puneet Gupta , Andrew B. Kahng, Manufacturing-Aware Physical Design, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.681, November 09-13, 2003 [doi>10.1109/ICCAD.2003.94]
• 12: L. He, A. B. Kahng, K. Tam, and J. Xiong, "Design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization," in Proc. SPIE Microlithography, Mar 2005.
• 13: T. E. Gbondo-Tugbawa, Chip-Scale Modeling of Pattern Dependencies in Copper Chemical Mechanical Polishing Process. PhD thesis, Massachusetts Institute of Technology, 2002.
• 14: "Quickcap user manual," in http://www.magma-da.com/.
• 15: R. Tian, D. Wong, and R. Boone, "Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, pp. 902--910, 2001.
• 16: J. Cong, L. He, C. Koh, and Z. Pan, "Interconnect sizing and spacing with considering of coupling capacitance," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp. 1164--1169, 2001.
• 17: H. Bakoglu, Circuits, Interconnects and Packaging for VLSI. Addison-Wesley, 1990.
• 18: C. Alpert, D. Devgan, and C. Kashyap, "Rc delay metrics for performance optimization," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 5, pp. 571--582, 2001.
• 19: K. Agarwal, D. Sylvester, and D. Blauuw, "A simple metric for rc circuit based on two circuit moments," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 9, pp. 1346--1354, 2004.
• 20: Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2003.
• 21: "Berkeley predictive technology model," in http://www-device.eecs.berkeley.edu/ ptm.
• 22: R.-S. Tsay, "An exact zero-skew clock routing algorithm," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-12, pp. 242--249, Feb. 1993.
• 23: Y. Cao, P. Gupta, A. Kahng, D. Sylvester, and J. Yang, "Design sensitivities to variability: Extrapolations and assessments in nanometer vlsi," in ASIC/SOC Conference, Sept 2002.
• 24: N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. Addison-Wesley, 2004.
• 25: A. Leon-Garcia, Probability and Random Processes for Electrical Engineering. Addison-Wesley, 1994.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design, Reliability

Keywords:
buffering, chemical mechanical polishing (CMP), design for manufacturing, wire sizing, yield