A localizing directory coherence protocol

ABSTRACT

User-controllable coherence revives the idea of cooperation between software and hardware in an attempt to bridge the gap between efficient small-scale shared memory machines and massive distributed memory machines. It proposes a new multiprocessor architecture which has both a global address-space and multiple processor-local address-spaces with new memory instructions and a new coherence protocol to manage the dual address-spaces.The purpose of this paper is twofold. First, we solidify the semantics of instruction set extensions that enable "localization" -- the act of moving data from the global address-space to a processor's local address-space -- thus clearly defining the requirements for a localizing coherence protocol. Second, we demonstrate the feasibility of localizing coherence by describing the workings of a full-scale directory-based protocol that we have implemented and tested using an existing protocol specification tool.

REFERENCES

• 1: Mark D. Hill , James R. Larus , Steven K. Reinhardt , David A. Wood, Cooperative shared memory: software and hardware for scalable multiprocessors, ACM Transactions on Computer Systems (TOCS), v.11 n.4, p.300-318, Nov. 1993 [doi>10.1145/161541.161544]
• 2: Collin McCurdy , Charles Fischer, User-controllable coherence for high performance shared memory multiprocessors, Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming, June 11-13, 2003, San Diego, California, USA
• 3: María Jesús Garzarán , Milos Prvulovic , Ye Zhangy , Josep Torrellas , Alin Jula , Hao Yu , Lawrence Rauchwerger, Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors, Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, p.243, September 08-12, 2001
• 4: Manoj Plakal , Daniel J. Sorin , Anne E. Condon , Mark D. Hill, Lamport clocks: verifying a directory cache-coherence protocol, Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures, p.67-76, June 28-July 02, 1998, Puerto Vallarta, Mexico [doi>10.1145/277651.277672]
• 5: David E. Culler , Anoop Gupta , Jaswinder Pal Singh, Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1997
• 6: Daniel J. Sorin , Manoj Plakal , Anne E. Condon , Mark D. Hill , Milo M. K. Martin , David A. Wood, Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol, IEEE Transactions on Parallel and Distributed Systems, v.13 n.6, p.556-578, June 2002 [doi>10.1109/TPDS.2002.1011412]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Hardware/software interfaces

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.4 Parallel Architectures

  D. Software
  D.1 PROGRAMMING TECHNIQUES
      D.1.3 Concurrent Programming
          Subjects: Parallel programming

General Terms:
Design, Performance

Keywords:
distributed memory architectures, irregular computation, parallel computation, shared memory architectures