| Multilevel full-chip routing with testability and yield enhancement |
| Full text |
Pdf
(369 KB)
|
| Source
|
International Workshop on System-Level Interconnect Prediction
archive
Proceedings of the 2005 international workshop on System level interconnect prediction
table of contents
San Francisco, California, USA
SESSION: Interconnect optimization
table of contents
Pages: 29 - 36
Year of Publication: 2005
ISBN:1-59593-033-7
|
|
Authors
|
|
Katherine Shu-Min Li
|
National Chiao Tung University, Hsichu, Taiwan
|
|
Chung-Len Lee
|
National Chiao Tung University, Hsichu, Taiwan
|
|
Yao-Wen Chang
|
National Taiwan University, Taipei, Taiwan
|
|
Chauchin Su
|
National Chiao Tung University, Hsichu, Taiwan
|
|
Jwu-E Chen
|
National Central University, Chungli, Taiwan
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 0
|
|
|
ABSTRACT
We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) The oscillation ring (OR) test and its diagnosis scheme for interconnect based on the IEEE P1500 are integrated into the multilevel routing framework to achieve testability enhancement. (2) We present a heuristic to balance routing congestion to optimize the multiple-fault probability, chemical mechanic polishing (CMP) and optical proximity correction (OPC) induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the MCNC benchmark circuits show that the proposed OR method achieves 100% fault coverage and the maximal diagnosis resolution for interconnects, and the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion. Compared with [14], the experimental results show that our router improves the maximal congestion by 1.24X--6.11X in runtime speedup by 1.08X--7.66X, and improves the average congestion by 1.00X--4.52X with the improved congestion deviation by 1.37X--5.55X.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 2001.
|
 |
2
|
|
 |
3
|
|
| |
4
|
G. Nanz and L. E. Camilletti, "Modeling of chemical-mechanical polishing: a review," IEEE Trans. Semiconductor Manufacturing, vol. 8, no. 4, pp. 382--389, 1995.
|
| |
5
|
L.-D Huang, M.D.F.Wong, "Optical Proximity Correction (OPC)-Friendly Maze Routing," in Proc. DAC, pp. 812--817, Jun. 2003."
|
| |
6
|
|
| |
7
|
C. J. Alpert, J.-H. Huang, and A. B. Kahng, "Multilevel circuit partitioning," IEEE Trans. on CAD, vol. 17, no. 8, pp. 655--667, Aug. 1998.
|
| |
8
|
|
| |
9
|
|
| |
10
|
S.-C. Lee, Y.-W. Chang, J.-M. Hsu, and H. Yang, "Multilevel large-scale module floorplanning/placement using B*-trees," in Proc. DAC, pp. 812--817, Jun. 2003.
|
| |
11
|
M. Hayashi and S. Tsukiyama, "A hybrid hierarchical global router for multi-layer VLSI's," IEICE Trans. Fundamentals, Vol. E78-A, No. 3, pp. 337--344, 1995.
|
| |
12
|
Y.-L. Lin, Y.-C. Hsu, and F.-S. Tsai, "Hybrid routing," IEEE Trans. on CAD, Vol. 9, No. 2, pp. 151--157, Feb. 1990.
|
 |
13
|
|
 |
14
|
|
|