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Image processing library for reconfigurable computers (abstract only)
Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays table of contents
Monterey, California, USA
POSTER SESSION: Novel applications of reconfigurability table of contents
Pages: 276 - 276  
Year of Publication: 2005
ISBN:1-59593-029-9
Authors
Mohamed Taher  The George Washington University, Washington DC
Esam El-Araby  The George Washington University, Washington DC
Tarek El-Ghazawi  The George Washington University, Washington DC
Kris Gaj  George Mason University, Fairfax, VA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Reconfigurable Computers (RCs) are parallel systems that are designed around multiple general-purpose processors and multiple field programmable gate array (FPGA) chips. These systems can leverage the synergism between conventional processors and FPGAs to provide low-level hardware functionality at the same level of programmability as general-purpose computers. RCs have proposed very high processing capabilities for computationally intensive applications such as Image Processing. This is due to the inherently parallel operation paradigm of the FPGA hardware.In this paper we present the design and implementation of image processing kernels for RCs. This library of kernels have been tested and verified for performance on one of the state-of-the-art reconfigurable computers, SRC-6E. This paper shows that RCs are between 8 to 400 times faster than comparable Pentiums for image based tasks.

Collaborative Colleagues:
Mohamed Taher: colleagues
Esam El-Araby: colleagues
Tarek El-Ghazawi: colleagues
Kris Gaj: colleagues