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3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only)
Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays table of contents
Monterey, California, USA
POSTER SESSION: FPGA architectures and circuits table of contents
Pages: 270 - 270  
Year of Publication: 2005
ISBN:1-59593-029-9
Authors
Chul Kim  Edith Cowan University, Joondalup, Australia
Alex Rassau  Edith Cowan University, Joondalup, Australia
Mike Myung-Ok Lee  Dongshin University, Republic of Korea
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper introduces a novel 3-Dimensional (3D) vertically integrated adaptive computing system. This 3D-SoftChip is a combination of state-of-the-art processing and interconnection technology. It comprises the vertical integration of two chips (a Configurable Array Processor and an Intelligent Configurable Switch) through indium bump 3D interconnections. The Configurable Array Processor (CAP) is an array of heterogeneous processing elements (PEs) while the Intelligent Configurable Switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer along with a Direct Memory Access (DMA) controller. This paper introduces the 3D-Softchip architecture for real-time communication and multimedia signal processing as a next generation computing system and describes the HW/SW codesign and verification methodology using SystemC.

Collaborative Colleagues:
Chul Kim: colleagues
Alex Rassau: colleagues
Mike Myung-Ok Lee: colleagues