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An execution environment for reconfigurable computing (abstract only)
Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays table of contents
Monterey, California, USA
POSTER SESSION: New CAD techniques and methods table of contents
Pages: 267 - 267  
Year of Publication: 2005
ISBN:1-59593-029-9
Authors
W. Fu Fu  University of Wisconsin, Madison, WI
K. Compton  University of Wisconsin, Madison, WI
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Although the benefits of software acceleration using reconfigurable logic have been demonstrated repeatedly, this style of computing has not yet penetrated the mainstream. One of the biggest unsolved problems is the management of the reconfigurable hardware in a multi-threaded environment. While most research in reconfigurable computing has assumed a single-threaded model, this is unrealistic for both personal computing and many types of embedded computing. In these cases, there may be several different threads running simultaneously. Each of these threads may have one or more sections of code (kernels) which would benefit from hardware acceleration. Somehow the operating system must decide at runtime which kernels to implement in software vs. hardware based on the status of the system. This includes potentially choosing from multiple possible hardware implementations (with different area/delay tradeoffs) of a single kernel. This paper examines our vision of reconfigurable computing applications in mainstream multithreaded systems, including a presentation of a proposed scheduling algorithm for allocating the reconfigurable hardware.