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ABSTRACT

Although runtime dynamic reconfiguration of the FPGA devices has been an issue of the last decade, it has yet to achieve general recognition by the design community. The reasons for this are clear; there exists no straightforward design methodology, and the partitioning and CAD tool support is poor. This paper presents general concepts implemented in a placement and routing tool that provides an environment where designs that are partially and dynamically reconfigurable can be processed in order to be implemented on FPGAs that support this technology, such as the Atmel AT40K and AT94K series. The function of the tool is demonstrated on a simple real-world example.