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Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform
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Source Architectural Support for Programming Languages and Operating Systems archive
Proceedings of the 11th international conference on Architectural support for programming languages and operating systems table of contents
Boston, MA, USA
SESSION: Potpourri table of contents
Pages: 144 - 155  
Year of Publication: 2004
ISBN:1-58113-804-0
Also published in ...
Authors
Perry H. Wang  Intel Corp.
Jamison D. Collins  Intel Corp.
Hong Wang  Intel Corp.
Dongkeun Kim  Intel Corp. and University of Maryland, College Park, MD
Bill Greene  Intel Corp.
Kai-Ming Chan  Intel Corp.
Aamir B. Yunus  Intel Corp.
Terry Sych  Intel Corp.
Stephen F. Moore  Intel Corp.
John P. Shen  Intel Corp.
Sponsors
SIGPLAN: ACM Special Interest Group on Programming Languages
SIGOPS: ACM Special Interest Group on Operating Systems
SIGARCH: ACM Special Interest Group on Computer Architecture
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 8,   Downloads (12 Months): 115,   Citation Count: 8
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ABSTRACT

Helper threading is a technology to accelerate a program by exploiting a processor's multithreading capability to run ``assist'' threads. Previous experiments on hyper-threaded processors have demonstrated significant speedups by using helper threads to prefetch hard-to-predict delinquent data accesses. In order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (VMT), a novel form of switch-on-event user-level multithreading, capable of fly-weight multiplexing of event-driven thread executions on a single processor without additional operating system support. The compiler plays a key role in minimizing synchronization cost by judiciously partitioning register usage among the user-level threads. The VMT approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread would be otherwise stalled.The concept of VMT is prototyped on an Itanium ® 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors. On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads, ranging from single-threaded workstation benchmarks to heavily multithreaded large scale decision support systems (DSS) using the IBM DB2 Universal Database. We measure a wall-clock speedup of 5.8% to 38.5% for the workstation benchmarks, and 5.0% to 12.7% on various queries in the DSS workload.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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CITED BY  8

Collaborative Colleagues:
Perry H. Wang: colleagues
Jamison D. Collins: colleagues
Hong Wang: colleagues
Dongkeun Kim: colleagues
Bill Greene: colleagues
Kai-Ming Chan: colleagues
Aamir B. Yunus: colleagues
Terry Sych: colleagues
Stephen F. Moore: colleagues
John P. Shen: colleagues