Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems

ABSTRACT

In embedded multithreaded architectures, the performance enhancement relative to the base single-threaded architecture is highly dependent on the characteristics of the application and memory configuration. When the application is well parallelized, the multithreading performance may be good even with a small cache since the memory access latency can be hidden. However, if there are complicated dependencies between threads, they cause frequent cache conflicts, so the performance may not be improved. For that reason, not only processor architecture but also memory configuration should be customized to get an optimal solution of an embedded multithreaded system. We suggest a design space exploration algorithm, which considers both memory configuration and multithreaded architecture and a thread shifting technique, which shifts threads in compile time to minimize cache conflict.

REFERENCES

• 1: S. Hily , A. Seznec, Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading, Proceedings of the 5th International Symposium on High Performance Computer Architecture, p.64, January 09-12, 1999
• 2: Rohit Jain , Christopher J. Hughes , Sarita V. Adve, Soft Real- Time Scheduling on Simultaneous Multithreaded Processors, Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS'02), p.134, December 03-05, 2002
• 3: Gautham K. Dorai , Donald Yeung, Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance, Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques, p.30, September 22-25, 2002
• 4: Hirst, K. R., Haskins, J. W., and Skadron, K. dMT: inexpensive throughput enhancement in small-scale embedded microprocessors with differential multithreading. IEE Proc.-Comput. Digit. Tech., vol. 151, no. 1, Jan. 2004.
• 5: Hily, S., and Seznec. A. Standard memory hierarchy does not fit simultaneous multithreading. In Proceedings of the Workshop on Multithreaded execution architecture and compilation (MTEAC), 1998.
• 6: Rakesh Kumar , Dean M. Tullsen, Compiling for instruction cache performance on a multithreaded architecture, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 7: Panda, P. R., Dutt, N. D., and Nicolau, A. Local memory exploration and optimization in embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 18, no. 1, Jan. 1999.
• 8: Chuanjun Zhang , Frank Vahid , Walid Najjar, A highly configurable cache architecture for embedded systems, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 9: Jörg Henkel , Yanbing Li, Avalanche: an environment for design space exploration and optimization of low-power embedded systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.454-468, August 2002 [doi>10.1109/TVLSI.2002.800524]
• 10: Wittenburg, J. P, Pirsch, P., and Meyer, G. A multithreaded architecture approach to parallel DSPs for high performance image processing applications. In Proceedings of the IEEE workshop on Signal processing systems (SiPS'99), 1999.
• 11: Heiko Oehring , Ulrich Sigmund , Theo Ungerer, MPEG-2 Video Decompression on Simultaneous Multithreaded Multimedia Processors, Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, p.11, October 12-16, 1999
• 12: Sigmund, U., Steinhaus, M., and Ungerer, T. On performance, transistor count and chip space assessment of multimedia-enhanced simultaneous multithreaded processors, In Proceedings of the Workshop on Multithreaded execution architecture and compilation (MTEAC-4), 2000.
• 13: James Burns , Jean-Luc Gaudiot, Area and System Clock Effects on SMT/CMP Processors, Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, p.211, September 08-12, 2001
• 14: Lucas Roh , Walid A. Najjar, Design of storage hierarchy in multithreaded architectures, Proceedings of the 28th annual international symposium on Microarchitecture, p.271-278, November 29-December 01, 1995, Ann Arbor, Michigan, United States
• 15: Lioupis, D., and Milios, S. Exploring cache performance in multithreaded processors, Microprocessors and Microsystems, vol.20, no.10, Jun. 1997.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)

Additional Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Microprocessor/microcomputer applications

General Terms:
Algorithms, Design, Performance

Keywords:
SMT, design space exploration, embedded systems, simultaneous multithreading