ACM Home Page
Please provide us with feedback. Feedback
Balancing design options with Sherpa
Full text PdfPdf (292 KB)
Source International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems table of contents
Washington DC, USA
SESSION: Application specific processors table of contents
Pages: 57 - 68  
Year of Publication: 2004
ISBN:1-58113-890-3
Authors
Timothy Sherwood  University of California, Santa Barbara
Mark Oskin  University of Washington
Brad Calder  University of California, San Diego
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 26,   Citation Count: 4
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1023833.1023843
What is a DOI?

ABSTRACT

Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, there have been several major projects that attempt to automate the process of transforming a predetermined processor configuration into a low level description for fabrication. These projects either leave the specification of the processor to the designer, which can be a significant engineering burden, or handle it in a fully automated fashion, which completely removes the designer from the loop.In this paper we introduce a technique for guiding the design and optimization of application specific processors. The goal of the Sherpa design framework is to automate certain design tasks and provide early feedback to help the designer navigate their way through the architecture design space. Our approach is to decompose the overall problem of choosing an optimal architecture into a set of sub-problems that are, to the first order, independent. For each sub-problem, we create a model that relates performance to area. From this, we build a constraint system that can be solved using integer-linear programming techniques, and arrive at an ideal parameter selection for all architectural components. Our approach only takes a few minutes to explore the design space allowing the designer or compiler to see the potential benefits of optimizations rapidly. We show that the expected performance using our model correlates strongly to detailed pipeline simulations, and present results showing design tradeoffs for several different benchmarks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
 
2
3
 
4
ARC. Whitepaper: Customizing a soft microprocessor core. http://www.arccores.com, 2001.
5
 
6
M. Berkelaar. lp solve: a mixed integer linear program solver. ftp://ftp.es.ele.tue.nl/pub/lp_solve, September 1997.
 
7
D. C. Burger and T. M. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
8
 
9
10
 
11
T. Givargis and F. Vahid. Platune: A tuning framework for system-on-a-chip platforms. IEEE Transactions on Computer Aided Design, 21(11), November 2002.
 
12
 
13
14
15
 
16
E. Lawler and D. Wood. Branch and bound methods: A survey. Operations Research, 14(291):699--719, 1966.
 
17
S. Leibson. Xscale (strongarm-2) muscles in. Microprocessor Report, September 2000.
 
18
T. Morimoto, K. Saito, H. Nakamura, T. Boku, and K. Nakazawa. Advanced processor design using hardware description language aidl. In In Proceedings of Asia and South Pacific Desing Automation Conference 1997 (ASP--DAC 1997), pages 387--390, 1997.
 
19
J. Mulder. An area model for on-chip memories and its applications. IEEE Journal of Solid States Circuits, 26(2):98--106, February 1991.
20
 
21
G. Reinman and N. Jouppi. Cacti version 2.0. http://www.research.digital.com/wrl/people/jouppi/CACTI.html, June 1999.
 
22
S. Santhanam. Strongarm 110: A 160mhz 32b 0.5w cmos arm processor. In Proceedings of HotChips VIII, pages 119--130, 1996.
23
 
24
C. Snyder. Synthesizable core makeover: Is lexra's seven-stage pipelined core the speed king? In Microprocessor Report, June 2001.
 
25
C.D. Snyder. Fpga processors cores get serious. Microprocessor Report, 14(9), September 2000.
26
27
 
28
S. Wilton and N. Jouppi. Cacti: An enhanced cache access and cycle time model. In IEEE Journal of Solid-State Circuits, May 1996.
29


Collaborative Colleagues:
Timothy Sherwood: colleagues
Mark Oskin: colleagues
Brad Calder: colleagues