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A low power architecture for embedded perception
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Source International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems table of contents
Washington DC, USA
SESSION: Application specific processors table of contents
Pages: 46 - 56  
Year of Publication: 2004
ISBN:1-58113-890-3
Authors
Binu Mathew  University of Utah, Salt Late City, UT
Al Davis  University of Utah, Salt Late City, UT
Mike Parker  University of Utah, Salt Late City, UT
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of complex perception applications cannot be met by current embedded processors and often even exceed the performance of high performance microprocessors whose energy consumption far exceeds embedded energy budgets. Though custom ASICs provide a solution to this problem, they incur expensive and lengthy design cycles and are inflexible. This paper introduces a VLIW perception processor which uses a combination of clustered function units, compiler controlled dataflow and compiler controlled clock-gating in conjunction with a scratch-pad memory system to achieve high performance for perceptual algorithms at low energy consumption. The architecture is evaluated using ten benchmark applications taken from complex speech and visual feature recognition, security, and signal processing domains. The energy-delay product of a 0.13μ implementation of this architecture is compared against ASICs and general purpose processors. Using a combination of Spice simulations and real processor power measurements, we show that the cluster running at 1 GHz clock frequency outperforms a 2.4 GHz Pentium 4 by a factor of 1.75 while simultaneously achieving 159 times better energy delay product than a low power Intel XScale embedded processor.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Binu Mathew: colleagues
Al Davis: colleagues
Mike Parker: colleagues