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Current flattening in software and hardware for security applications
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International Conference on Hardware Software Codesign archive
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis table of contents
Stockholm, Sweden
SESSION: New techniques for security and reliability enhancement in embedded systems table of contents
Pages: 218 - 223  
Year of Publication: 2004
ISBN:1-58113- 937-3
Authors
Radu Muresan  University of Guelph, Guelph, Ontario, Canada
Catherine Gebotys  University of Waterloo, Waterloo, Ontario, Canada
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
SIGBED: ACM Special Interest Group on Embedded Systems
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 10,   Downloads (12 Months): 29,   Citation Count: 4
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ABSTRACT

This paper presents a new current flattening technique applicable in software and hardware. This technique is important in embedded cryptosystems since power analysis attacks (that make use of the current variation dependency on data and program) compromise the security of the system. The technique flattens the current internally by exploiting current consumption differences at the instruction level. Code transformations supporting current variation reductions due to program dependencies are presented. Also, a new real-time hardware architecture capable of reducing the current to data and program dependencies is proposed. Measured and simulated current waveforms of cryptographic software are presented in support of these techniques.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Gebotys, C., Design of secure encryption in dsp embedded processors. In Proceedings of DATE, 2002.
 
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Kocher, P., Jaffe, J., and Jun, B., Introduction to differential power analysis and related attacks. Technical Report. http://www.cryptography.com/dap/technical, 1998.
 
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Kommerling, O., Kuhn, M. G., Design principles for tamper-resistant smartcard processors. In Proceedings of the USENIX Workshop on Smartcard Technology (Smartcard '99), Chicago, May 1999, pp. 9--20.
 
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Motorola Inc., StarCore 140 Software Development Platform. Hardware Reference Manual, Motorola, April 2000.
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Collaborative Colleagues:
Radu Muresan: colleagues
Catherine Gebotys: colleagues