| Multi-objective mapping for mesh-based NoC architectures |
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International Conference on Hardware Software Codesign
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Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
table of contents
Stockholm, Sweden
SESSION: NoC design and optimisation
table of contents
Pages: 182 - 187
Year of Publication: 2004
ISBN:1-58113- 937-3
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Downloads (6 Weeks): 7, Downloads (12 Months): 94, Citation Count: 11
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ABSTRACT
In this paper we present an approach to multi-objective exploration of the mapping space of a mesh-based network-on-chip architecture. Based on evolutionary computing techniques, the approach is an efficient and accurate way to obtain the Pareto mappings that optimize performance and power consumption. Integration of the approach in an exploration framework with a kernel based on an event-driven trace-based simulator makes it possible to take account of important dynamic effects that have a great impact on mapping. Validation on both synthesized traffic and real applications (an MPEG-2 encoder/decoder system) confirms the efficiency, accuracy and scalability of the approach.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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A. Hemani , T. Meincke , S. Kumar , A. Postula , T. Olsson , P. Nilsson , J. Oberg , P. Ellervee , D. Lundqvist, Lowering power consumption in clock by using globally asynchronous locally synchronous design style, Proceedings of the 36th ACM/IEEE conference on Design automation, p.873-878, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.310091]
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Santiago Gonzalez Pestana , Edwin Rijpkema , Andrei Rdulescu , Kees Goossens , Om Prakash Gangwal, Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach, Proceedings of the conference on Design, automation and test in Europe, p.20764, February 16-20, 2004
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E. Zitzler, M. Laumanns, and L. Thiele. SPEA2: Improving the performance of the strength pareto evolutionary algorithm. In Evolutionary Methods for Design, Optimization and Control with Applications to Industrial Problems, pages 95--100, Athens, Greece, Sept. 2001.
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CITED BY 11
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Gianluca Palermo , Giovanni Mariani , Cristina Silvano , Riccardo Locatelli , Marcello Coppola, A topology design customization approach for STNoC, Proceedings of the 2nd international conference on Nano-Networks, September 24-26, 2007, Catania, Italy
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Maurizio Palesi , Giuseppe Longo , Salvatore Signorino , Rickard Holsmark , Shashi Kumar , Vincenzo Catania, Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.97-106, April 07-10, 2008
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