Take a look at the new version of this page: [ beta version ]. Tell us what you think.

ABSTRACT

One of the main problems when designing large ASICs today is to distribute a low power synchronous clock over the whole chip and a lot of remedies to this problem has been proposed over the years. For Networks-on-Chip (NoC), where computational Resources are organised in a 2-D mesh connected together through Switches in an on-chip interconnection network, another possibility exists: Globally Pseudochronous Locally Synchronous clock distribution.In this paper, we present a clocking scheme for NoCs that we call Globally Pseudochronous Locally Synchronous, in which we distribute a clock with a constant phase difference between the switches. As a consequence of the phase difference, some paths along the NoC switch network become faster than the others. We call these paths Data Motorways. By adapting the switching policy in the switches to prefer data to use the motorways, we show that the latency within the network is reduced with up to 40% compared to a synchronous reference case.The phase difference between the resources also makes the circuit more tolerant to clock skew. It also distributes the current peaks more evenly across the clock period, which lead to a reduction in peak power, which in turn further reduces the clock skew and the jitter in the clock network.

REFERENCES

• 1: The International Technology Roadmap for Semiconductors. Semiconductor Industry Association, International SEMATECH:Austin, TX., 2001.
• 2: C. Anderson. Physical design of a fourth-generation POWER GHz microprocessor. In Solid-State Circuits Conference, 2001.
• 3: William J. Dally , John W. Poulton, Digital systems engineering, Cambridge University Press, New York, NY, 1998
• 4: E. Friedman. Clock distribution networks in synchronous digital integrated circuits. Proceedings of the IEEE, 2001.
• 5: A. Hemani , T. Meincke , S. Kumar , A. Postula , T. Olsson , P. Nilsson , J. Oberg , P. Ellervee , D. Lundqvist, Lowering power consumption in clock by using globally asynchronous locally synchronous design style, Proceedings of the 36th ACM/IEEE conference on Design automation, p.873-878, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310091]
• 6: R. Ho, K. Mai, and M. Horowitz. The future of wires. Proceedings of the IEEE, 2001.
• 7: Jiang Xu , Wayne Wolf, Wave pipelining for application-specific networks-on-chips, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France [doi>10.1145/581630.581661]
• 8: J. Liu, L.-R. Zheng, D. Pamunawa, and H. Tenhunen. A global wire planning scheme for network-on-chip. In IEEE International Symposium on Circuits and Systems (ISCAS), Proceedings of, 2003.
• 9: F. Mu and C. Svensson. Self-tested self-synchronization circuit for mesochronous clocking. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2001.
• 10: Erland Nilsson , Mikael Millberg , Johnny Oberg , Axel Jantsch, Load Distribution with the Proximity Congestion Awareness in a Network on Chip, Proceedings of the conference on Design, Automation and Test in Europe, p.11126, March 03-07, 2003
• 11: Frank O'Mahony , C. Patrick Yue , Mark A. Horowitz , S. Simon Wong, Design of a 10GHz clock distribution network using coupled standing-wave oscillators, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.776005]
• 12: I. Soderquist. Globally updated mesochronous design style. IEEE Journal of Solid-State Circuits, 2003.
• 13: J. Wood, T. Edwards, and S. Lipa. Rotary traveling-wave oscillator arrays: a new clock technology. Solid-State Circuits, IEEE Journal of, 2001.
• 14: Qing K. Zhu, High-Speed Clock Network Design, Kluwer Academic Publishers, Norwell, MA, 2002
• 15: Johnny Öberg, Clocking strategies for networks-on-chip, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

General Terms:
Design

Keywords:
GALS, GPLS, clocking, hot-potato, mesh, network on chip, pseudochronous