Power-aware communication optimization for networks-on-chips with voltage scalable links

ABSTRACT

Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energy-efficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoC-based systems, including task assignment, tile mapping, routing path allocation, task scheduling and link speed assignment. Experimental results show that the proposed design technique can reduce energy consumption by 28% on average compared with existing techniques.

REFERENCES

• 1: Luca Benini , Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, Computer, v.35 n.1, p.70-78, January 2002 [doi>10.1109/2.976921]
• 2: Xuning Chen , Li-Shiuan Peh, Leakage power modeling and optimization in interconnection networks, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871531]
• 3: William J. Dally , Brian Towles, Route packets, net wires: on-chip inteconnectoin networks, Proceedings of the 38th conference on Design automation, p.684-689, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379048]
• 4: Jose Duato , Sudhakar Yalamanchili , Lionel Ni, Interconnection Networks: An Engineering Approach, IEEE Computer Society Press, Los Alamitos, CA, 1997
• 5: Jingcao Hu , Radu Marculescu, Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.10688, March 03-07, 2003
• 6: J. Kim and M. Horowitz. Adaptive Supply Serial Links with Sub-1V Operation and Per-pin Clock Recovery. In Proc. International Solid-State Circuits Conference, 2002.
• 7: Tang Lei , Shashi Kumar, A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture, Proceedings of the Euromicro Symposium on Digital Systems Design, p.180, September 01-06, 2003
• 8: I. M. Oliver , D. J. Smith , J. R. C. Holland, A study of permutation crossover operators on the traveling salesman problem, Proceedings of the Second International Conference on Genetic Algorithms on Genetic algorithms and their application, p.224-230, October 1987, Cambridge, Massachusetts, United States
• 9: Jennifer Rexford , John Hall , Kang G. Shin, A router architecture for real-time point-to-point networks, Proceedings of the 23rd annual international symposium on Computer architecture, p.237-246, May 22-24, 1996, Philadelphia, Pennsylvania, United States
• 10: Marcus T. Schmitz , Bashir M. Al-Hashimi, Considering power variations of DVS processing elements for energy minimisation in distributed systems, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada [doi>10.1145/500001.500060]
• 11: Li Shang , Li-Shiuan Peh , Niraj K. Jha, Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks, Proceedings of the 9th International Symposium on High-Performance Computer Architecture, p.91, February 08-12, 2003
• 12: T. Simunic , S. Boyd, Managing Power Consumption in Networks on Chip, Proceedings of the conference on Design, automation and test in Europe, p.110, March 04-08, 2002
• 13: V. Soteriou and L.-S. Peh. Dynamic Power Management for Power Optimization of Interconnection Networks Using On/Off Links. In Proc. Symposium on High Performance Interconnects, pages 15--20, 2003.
• 14: Hangsheng Wang , Li-Shiuan Peh , Sharad Malik, Power-driven Design of Router Microarchitectures in On-chip Networks, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.105, December 03-05, 2003
• 15: Frédéric Worm , Paolo Ienne , Patrick Thiran , Giovanni De Micheli, An adaptive low-power transmission scheme for on-chip networks, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan [doi>10.1145/581199.581221]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

General Terms:
Algorithms, Design

Keywords:
low-power design, network-on-chip, real-time systems