Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

ABSTRACT

In multiprocessor based SoCs, optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time; at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation level concurrency maps to the microarchitectural level concurrency. This paper presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication sub-system through a rigorous modeling approach based on a formal concurrency model, the Operation State Machine (OSM). We first introduce the basic notions and concepts of OSM and show by example how this model can be used to represent the inherent concurrency in the architecture and microarchitecture of processors. Then we demonstrate the applicability of OSM in modeling on-chip communication architectures (OCAs) by walking though a router based packet switching network example and a bus example. Due to the fact that the OSM model is naturally suited to handle the operation and microarchitecture level concurrencies of OCAs as well, our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multi-PE SoC prototypes. To demonstrate the flexibility of this methodology, we choose two distinct system configurations with different types of OCA: a 4x4 mesh network of 16 PEs, and a cluster of 4 PEs connected by a bus. We show that by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design. In addition to improving design quality, this methodology also results in significantly shortened design-time.

REFERENCES

• 1: Released Simulator. http://www.princeton.edu/mescal/software.html.
• 2: Marcello Coppola , Stephane Curaba , Miltos D. Grammatikakis , Riccardo Locatelli , Giuseppe Maruccia , Francesco Papariello, OCCN: a NoC modeling framework for design exploration, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.2-3, p.129-163, February 2004 [doi>10.1016/j.sysarc.2003.07.002]
• 3: W. J. Dally, Virtual-Channel Flow Control, IEEE Transactions on Parallel and Distributed Systems, v.3 n.2, p.194-205, March 1992 [doi>10.1109/71.127260]
• 4: K. Fall and K. Varadhan. ns notes and documentation. The VINT Project, UC Berkeley, LBL, USC/ISI, Xerox PARC, 2000.
• 5: Erich Gamma , Richard Helm , Ralph Johnson , John Vlissides, Design patterns: elements of reusable object-oriented software, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1995
• 6: Antoine Jalabert , Srinivasan Murali , Luca Benini , Giovanni De Micheli, ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip, Proceedings of the conference on Design, automation and test in Europe, p.20884, February 16-20, 2004
• 7: Mirko Loghi , Federico Angiolini , Davide Bertozzi , Luca Benini , Roberto Zafalon, Analyzing On-Chip Communication in a MPSoC Environment, Proceedings of the conference on Design, automation and test in Europe, p.20752, February 16-20, 2004
• 8: Damien Lyonnard , Sungjoo Yoo , Amer Baghdadi , Ahmed A. Jerraya, Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip, Proceedings of the 38th conference on Design automation, p.518-523, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379015]
• 9: Mikael Millberg , Erland Nilsson , Rikard Thid , Axel Jantsch, Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip, Proceedings of the conference on Design, automation and test in Europe, p.20890, February 16-20, 2004
• 10: Pierre Paulin , Chuck Pilkington , Essaid Bensoudane, StepNP: A System-Level Exploration Platform for Network Processors, IEEE Design & Test, v.19 n.6, p.17-26, November 2002 [doi>10.1109/MDT.2002.1047740]
• 11: Wei Qin , Subramanian Rajagopalan , Sharad Malik, A formal concurrency model based architecture description language for synthesis of software development tools, Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, June 11-13, 2004, Washington, DC, USA
• 12: Michael Bedford Taylor , Jason Kim , Jason Miller , David Wentzlaff , Fae Ghodrat , Ben Greenwald , Henry Hoffman , Paul Johnson , Jae-Wook Lee , Walter Lee , Albert Ma , Arvind Saraf , Mark Seneski , Nathan Shnidman , Volker Strumpen , Matt Frank , Saman Amarasinghe , Anant Agarwal, The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs, IEEE Micro, v.22 n.2, p.25-35, March 2002 [doi>10.1109/MM.2002.997877]
• 13: Hang-Sheng Wang , Xinping Zhu , Li-Shiuan Peh , Sharad Malik, Orion: a power-performance simulator for interconnection networks, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 14: J. Wang. Petri Nets: Properties, Analysis and Applications. Kluwer Academic Publishers, Boston, MA, 1998.
• 15: Andreas Wieferink , Tim Kogel , Rainer Leupers , Gerd Ascheid , Heinrich Meyr , Gunnar Braun , Achim Nohl, A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms, Proceedings of the conference on Design, automation and test in Europe, p.21256, February 16-20, 2004
• 16: Xinping Zhu , Sharad Malik, A hierarchical modeling framework for on-chip communication architectures, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.663-671, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774670]
• 17: Xinping Zhu , Sharad Malik, Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing, Proceedings of the conference on Design, automation and test in Europe, p.21244, February 16-20, 2004

INDEX TERMS

Primary Classification:
  I. Computing Methodologies
  I.6 SIMULATION AND MODELING
      I.6.5 Model Development

Additional Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Design, Experimentation, Languages, Measurement, Performance, Verification

Keywords:
bus, design exploration, multiprocessor system, on-chip communication architecture, packet-switching network, retargetable simulation, simulator synthesis