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ABSTRACT

This work presents a method to design parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation with reduced number of adders and logic depth in the multiplier block. The proposed method uses a combination of two approaches: first, the reduction of the coefficients to N-Power-of-Two (NPT) terms, where N is the maximum number of bits in '1' state allowed for each coefficient and Common Subexpression Elimination (CSE) among multipliers. An algorithm for selecting the best NPT coefficient set for a given filter specification is proposed. Initially, a floating point coefficient set is generated using classical methods for FIR filters and then several sets of fixed point coefficients are generated by rounding the result of the floating point coefficients multiplied by a scale factor different for each set. The coefficient sets are then converted to NPT and a frequency response for each set is obtained. Based on the frequency response, the algorithm selects the best set. This set is then used as input for a CSE algorithm, which eliminate all common subexpressions among the multipliers and generates a hardware description of the filter in VHDL for synthesis purpose. The results show significant reduction in the number of adders and logic depth of the multiplier block with a minimal degradation in the filter transfer characteristics, showing the usefulness of the proposed method for low power design of parallel filters.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.1 Design Styles
          Subjects: Parallel

General Terms:
Algorithms, Experimentation, Performance

Keywords:
FPGA synthesis, common subexpression elimination, parallel FIR filter, power-of-two