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ABSTRACT

This paper presents the design of an ultra-low-power self-biased 400pA current source. An efficient design methodology has resulted in a cell area around 0.045mm² (0.027mm²) in the AMIS 1.5μm (TSMC 0.35μm) CMOS technology and power consumption around 2nW for 1.2V supply. Simulated and experimental results validate the design and show that the current sources can operate at supply voltages down to 1.1V with a good regulation (< 4%/V variation of the supply voltage in a 0.35μm technology). This current source is suitable for very-low-power applications.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.0 General

General Terms:
Design

Keywords:
current reference, design methodology, inversion level, low-voltage, self-cascode MOSFET, ultra-low-power